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Tobias Strauch, EDAptix
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The processor is the new transistor.
Tobias Strauch, EDAptix   7/22/2014 8:51:16 AM
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What looks scary to to me is that Xilinx is using a different parser for synthesis (Verific) and simulation (old-Modelsim), or am I wrong again so that I can sleep well at night, again ;-)

Certainly you have to simplify the diagram, but what I miss is a third branch of programmability, which is the multicore (or multiprocessor) domain. You can run complex algorithms down to timing critical virtual peripherals on such a processor arrays. I was wondering how the market will evolve for IP providers (such as Menta) for such a domain.

Cheers, Tobias

TonyTib
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Re: Heavy stuff
TonyTib   7/11/2014 2:41:11 PM
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Of course the Zynq is already <$15, you just have to buy the most basic model by the millions...

betajet
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Re: Heavy stuff
betajet   7/11/2014 2:09:33 PM
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ChristophZ wrote: We've seen the Virtex-II Pro and now Zinq ... which gives great flexiblity and potential performance boost.  But it is expensive...

We took a look at Virtex-II Pro back when it was fairly new.  Technologically it was a good fit for our product line, because we were using PowerPC CPUs.  However, Virtex-II Pro was way too expensive, with the cheapest chips over US$100 IIRC.  So instead we went with an IBM (now AMCC / Applied Micro) PPC405EP for about US$10 plus a Spartan-IIE for about US$15, using a 32-bit PCI bus to communicate between them.  Very nice solution, since both chips used +3.3V and +1.8V power.

I've been watching Zynq for a while now, still waiting for the price to come down.  The Xcell Journal article from 2Q2011 says "With a starting point below $15..."  I'm waiting for reality to catch up with marketing.  Meanwhile, Spartan-3A and Spartan-6 are nice architectures.

ChristophZ also wrote: ... and a lot of people don't need big FPGAs...

I hear you.  I would like a Spartan-6 LXT9 or LXT16 with PCI express, but the smallest Spartan-6 with PCIe is the LXT25.

Max The Magnificent
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Re: Shame on me!
Max The Magnificent   7/11/2014 9:31:50 AM
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@Garcia: By the way, I was taking a look to the Verific Design Automation web site and I've discovered they have quoted this blog in his front page!!

Happy Dance!!! :-)

Max The Magnificent
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Re: Shame on me!
Max The Magnificent   7/11/2014 9:31:14 AM
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@Garcia: I can't believe that this is the first time I read about Verific HDL parsers...

You never asked me :-)

Max The Magnificent
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Re: ADICSYS FPGAs
Max The Magnificent   7/11/2014 9:30:19 AM
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@alex_m1: This technology is interesting. Are there examples of real life products using it...

Until I get to talk with Peer, I'll ask him to answer this

Max The Magnificent
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Re: ADICSYS FPGAs
Max The Magnificent   7/11/2014 9:27:43 AM
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@Peer: In order to make the diagram more complete (last branch to the right), check us out at www.adicsys.com. ADICSYS has been designing and distributing embedded FPGAs and customized solutions implying generic RTL programmability for a few years now, not to mention our past FPGA activities.

Thanks for this info -- why haven't you contacted me before? LOL

Email me at max.maxfield@ubm.com and maybe we can set up a briefing where to bring me up to date with everything you are doing so I can write a column and spread the word :-)

Max The Magnificent
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Re: Heavy stuff
Max The Magnificent   7/11/2014 9:24:29 AM
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@ChristophZ: In a lot of current designs there are only a few big digital chips in it (the rest is mixed signal or only analog). But there is still need for some glue logic and special requirements.

Very (very) often, an SoC is accompanied by an FPGA that can be used to implement changes or problems or things that were left out of the original spec -- it really makes sense to me to include one or more chunks of FPGA fabric in the middle of the SoC.

Garcia-Lasheras
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eFPGA for ISM
Garcia-Lasheras   7/11/2014 7:45:41 AM
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I agree in that embedding FPGA as a companion peripheral inside a SoC is going to be one of the future trends to follow.

As a quick example, I can imagine the use of this technology in order to implement flexible industrial field bus interfaces. TI is already embedding a kind of programmable state machine real-time units is some of its SoCs (e.g. the Sitara AM335X family) that can be used to implement PROFIBUS, EtherCAT, PROFINET... I'm sure that a little FPGA core could be a killer-app in this arena!

Garcia-Lasheras
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Shame on me!
Garcia-Lasheras   7/11/2014 7:36:16 AM
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@Max: I can't believe that this is the first time I read about Verific HDL parsers... too bad for a skilled FPGA designer :-(

By the way, I was taking a look to the Verific Design Automation web site and I've discovered they have quoted this blog in his front page!!

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