Rick, a guy from zvi orbach's company talked about 3d chips as a strong way to fight defects. Self assembly and Molecular Imprints suffer strong defect rate, but at least they have the resolution. I wonder how well a combination will to solve the defect issue will work cost wise ?
a 2 x 64 bit bus carrying 25 GByte/s for LP DDR ( Dual Data Rate ) means a Clock Rate of 800 MHz, not at all unusual for LP DDR 3, it works even with conventional lossy Packages.
Apple has been using them for the 5s since last Fall, had to shrink Package interconnect pitch to accomodate wider channels, but that's still a conventional PoP package. SK Hynix claims their LP DDR 3 can run at Clock Rates double that but have n't seen a SoC - DRAM module packaged in conventional PoP working at 1.6 GHz yet.
We do special loss - less Packages that clean up the Eye Diagram even at much higher Clock Rates for very high Bandwidth and low Power loss w/o having to drill any TSVs into live chips.
"No matter what Intel says, Moore's Law is slowing down," said Bob Johnson, a semiconductor analyst for Gartner. "Only a few high-volume, high-performance apps can justify 20 nm and beyond." He sees problems ahead for logic chips in general. The smartphone market is nearing saturation, ultramobiles are canabalizing PCs, and "logic is running out of gas."
If logic is getting affected, that's a really big problem.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.