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resistion
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CEO
Re: EUV update
resistion   7/26/2014 10:52:00 PM
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The reason they changed to wafers per day, is not only that they cannot get enough wafers per hour, but also the EUV machine is not (or cannot be) up 100% of the day. So even if the WPH is quite reasonable, with the extended downtime, it still reduces the throughput, that is measured in wafers per day.

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/19/2014 6:33:31 AM
NO RATINGS
It's the right idea, it looks like you are referring to the example of double patterning using two exposures, for a single layer. More generally, overlay is referring to the interaction between successive layers, so that they link up properly. Multiple exposures does have higher risk than single exposure. But these recent new single-exposure technologies have their own sources contributing overlay error. Meanwhile multi-patterning is heading toward self-aligned approaches.

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/19/2014 6:25:50 AM
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When patterning a first layer, the features deviate from their positions within a tolerance. Then when the next layer is patterned over the first layer, those features also deviate from their positions within a tolerance. If the tolerances are followed, there should be no risk of broken connections, line shorts, etc.

rick merritt
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Author
Re: What did you hear?
rick merritt   7/18/2014 8:52:26 PM
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@Alex: I am no expert, but I assume it is when you are doing a second litho pattern for a critical dimension and it does not line up within given tolerances with the previous pattern.

Someone correct me if I am wrong.

alex_m1
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CEO
Re: What did you hear?
alex_m1   7/18/2014 4:28:53 AM
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What's an overlay error?

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/18/2014 2:18:04 AM
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Ok, but if there is an overlay error issue, especially from the new patterning technologies, then there's nothing that can be done.

alex_m1
User Rank
CEO
Re: What did you hear?
alex_m1   7/17/2014 12:54:33 PM
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@resistion:i think the case of 3-4 real logic layers + 1 repair layer might be interesting economically and might offer enough defence against defects to make those methods(self assmbly,imprints) useful.

 

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/17/2014 5:51:49 AM
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Thanks, alex_m1. The concept of this repair layer sounds interesting, but of course, it's still cheaper to have all the layers within defect tolerances to begin with (so then you could go on to heterogeneous integration).

alex_m1
User Rank
CEO
Re: What did you hear?
alex_m1   7/17/2014 2:43:53 AM
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Resistion: the way i understood it , you build 2 equivalent layers on top of one another, And for gate(or cell) you choose which layer 2 use after manufacturing - using boundary scan for detection and e-beam for the repair. more details in [1].


Assuming defects are uncorrelated between layers(big assumption), this greatly decreases you defect probability.

 

[1]http://www.monolithic3d.com/ultra-large-integration---redundancy-and-repair.html

resistion
User Rank
CEO
Re: EUV update
resistion   7/16/2014 11:16:19 PM
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The units for EUV throughput are really wafers per day, and 200 is the current capabilty: http://seekingalpha.com/article/2318615-asml-holdings-asml-ceo-peter-wennink-on-q2-2014-results-earnings-call-transcript?part=single

They would like to go to 500 this year and eventually 1500 wafers/day. Their immersion meanwhile already does >5000 wafers/day.

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