Breaking News
Comments
Oldest First | Newest First | Threaded View
Page 1 / 2   >   >>
rick merritt
User Rank
Author
What did you hear?
rick merritt   7/11/2014 10:29:27 AM
NO RATINGS
There was a ton of activity at the event and many talks I could not get to, so what did I miss?

resistion
User Rank
CEO
Thanks for the summary
resistion   7/11/2014 11:25:10 PM
NO RATINGS
Nice crisp summary, for those of us who can't go, perennially.

resistion
User Rank
CEO
Key takeaway
resistion   7/11/2014 11:42:13 PM
NO RATINGS
"No matter what Intel says, Moore's Law is slowing down," said Bob Johnson, a semiconductor analyst for Gartner. "Only a few high-volume, high-performance apps can justify 20 nm and beyond." He sees problems ahead for logic chips in general. The smartphone market is nearing saturation, ultramobiles are canabalizing PCs, and "logic is running out of gas."

If logic is getting affected, that's a really big problem.

chipmonk0
User Rank
CEO
Re. Item 5 : Heard the one about Snapdragon ?
chipmonk0   7/15/2014 8:26:20 PM
NO RATINGS
Is that such a big deal ?

a 2 x 64 bit bus carrying 25 GByte/s for LP DDR ( Dual Data Rate ) means a Clock Rate of 800 MHz, not at all unusual for LP DDR 3, it works even with conventional lossy Packages.

Apple has been using them for the 5s since last Fall, had to shrink Package interconnect pitch to accomodate wider channels, but that's still a conventional PoP package. SK Hynix claims their LP DDR 3 can run at Clock Rates double that but have n't seen a SoC - DRAM module packaged in conventional PoP working at 1.6 GHz yet.

We do special loss - less Packages that clean up the Eye Diagram even at much higher Clock Rates for very high Bandwidth and low Power loss w/o having to drill any TSVs into live chips.

alex_m1
User Rank
CEO
Re: What did you hear?
alex_m1   7/16/2014 6:09:27 PM
NO RATINGS
Rick, a guy from zvi orbach's company talked about 3d chips as a strong way to fight defects. Self assembly and  Molecular Imprints suffer strong defect rate, but at least they have the resolution. I wonder how well a combination will to solve the defect issue will work cost wise ?

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/16/2014 6:48:47 PM
NO RATINGS
How would 3d help defects? If redundancy, still need a defect-free die or part.

rick merritt
User Rank
Author
EUV update
rick merritt   7/16/2014 10:09:19 PM
NO RATINGS
ASML announced in its quarterly earnings call yesterday that EUV throughput with at least one customer is now up to 200 wafers/day.

Of course its wafers/HOUR which is really key. Waiting to hear back if they have any news on that.

The Q1 report was ~37 w/h and the target for commervcial use is more like 100+

resistion
User Rank
CEO
Re: EUV update
resistion   7/16/2014 11:16:19 PM
NO RATINGS
The units for EUV throughput are really wafers per day, and 200 is the current capabilty: http://seekingalpha.com/article/2318615-asml-holdings-asml-ceo-peter-wennink-on-q2-2014-results-earnings-call-transcript?part=single

They would like to go to 500 this year and eventually 1500 wafers/day. Their immersion meanwhile already does >5000 wafers/day.

alex_m1
User Rank
CEO
Re: What did you hear?
alex_m1   7/17/2014 2:43:53 AM
NO RATINGS
Resistion: the way i understood it , you build 2 equivalent layers on top of one another, And for gate(or cell) you choose which layer 2 use after manufacturing - using boundary scan for detection and e-beam for the repair. more details in [1].


Assuming defects are uncorrelated between layers(big assumption), this greatly decreases you defect probability.

 

[1]http://www.monolithic3d.com/ultra-large-integration---redundancy-and-repair.html

resistion
User Rank
CEO
Re: What did you hear?
resistion   7/17/2014 5:51:49 AM
NO RATINGS
Thanks, alex_m1. The concept of this repair layer sounds interesting, but of course, it's still cheaper to have all the layers within defect tolerances to begin with (so then you could go on to heterogeneous integration).

Page 1 / 2   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Steve Wozniak Reacts to Latest iPhone
Max Maxfield
5 comments
Funnily enough, just a few days ago as I pen these words, I was chatting with my wife (Gina the Gorgeous) when she informed me that -- as a kid -- she had never played at making a ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)