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chipmonk0
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Re: Stake in the ground
chipmonk0   7/15/2014 6:53:40 PM
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The development of TSV based 3-d stacks of chips has been slow ( at least 7 to 10 years ). Seasoned IDMs in the US with broad expertise did not participate since they were naturally more interested in pushing their latest Fabs to integrate a variety of functions on a single chip, not as mutiple chips in 2 or 3-d modules. So for the most part TSVs have been a very fragmented effort carried out at various Govt. funded Labs overseas, specially W. Europe since the process for etching straight walled through vias in Si originated at Bosch in Germany ( for MEMS ).  and a host of European tool vendors with limited horizon also joined in. Large Foundries in E. Asia depended on these Euro Labs for TSV tech but the latter proved not up to the challenges when it came to integrating Logic to Memory rather than just to MEMS. Key issues like via stress & heat accumulation effects on device performance were not recognized early on. Even material & process issues were not properly explored with the consequence that even today the filling of TSVs by Cu remains a matter of controversy, and materials & processes for bond / debond of thinned wafers remain in flux.

Recently Intel announced that starting sometime next year they will use Micron's 3-d stack DRAM ( HMC ) for high power Xeon server modules. This is a more logical niche for expensive new technology like 3-d TSV with technology risks before all the bugs are worked out and yield climbs to make it affordable for mass - market products that the likes of QualComm cater to.

But we still have to wait till late next year to see how soon Micron can get the yields of its HMC up and prices down.

rick merritt
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Re: Stake in the ground
rick merritt   7/15/2014 5:45:28 PM
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Yes, we have written a fair amount about 2.5- and 3-DICs.

The Qualcomm guy I talked to at Semicon West is still singing the same song I have heard from them for the last 2-3 years..."Make Using TSVs Cheaper!"

rick merritt
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Re: Where do $3B come from?
rick merritt   7/15/2014 3:15:02 PM
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An IBM rep told be the ~$600 million/year over the next five years represents ongoing work in existing programs. IBM has been at this stuff, on the leadig edge of much of it, for years.

And yes a lot of it is at TJ Watson in Yorktown Heights, Almanden research in San Jose and a handful of other labs in Europe and Israel.

geekmaster
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Where do $3B come from?
geekmaster   7/15/2014 1:34:05 PM
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I wonder where the $3B come from?
Also, if it drives R&D programs, then I assume that the Yorktown research facility will benefit from it. I am not sure this benefits in any way BTV with their legacy facilities.

vharihar
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Scaling reset
vharihar   7/15/2014 12:53:43 PM
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When the post-Si era starts (eg. III-V materials, or whatever), I actually believe that instead of starting from 5 nm (if Si were to stop at 5 nm) and continuing forth from there, dimensions will get reset to a bigger dimension, say 22 nm, assuming that the post-Si process development reaches a stage where it yields performance/power improvements at the larger dimension better than what the last Si process gave at 5 nm.

The move to a bigger dimension is desireable for process variation and yield standpoint.

And that new post-Si technology would again scale from 22 nm to smaller dimensions, until it too runs out of steam.

Just a thought.

arno_x
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Re: Stake in the ground
arno_x   7/15/2014 6:26:31 AM
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Hello Rick

there is already a new area coming now, the 3D packaging that might give the impression that "better, cheaper, faster stuff every two years" will keep on existing few more years (until 2030?...).

I guess the next step is integrating the proc, the memory and the chipset under the same package via TSV, and that might elongate or gives some time to the new processes for being released. For example "proc @ 10 nm + memory@ 14 nm +chipset @ 20 nm" then  "proc @ 10 nm + memory@ 10 nm +chipset @ 20 nm" then  "proc @ 10 nm + memory@ 10 nm +chipset @ 14 nm" and so on...

arno_x
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Re: Stake in the ground
arno_x   7/15/2014 6:26:28 AM
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Hello Rick

there is already a new area coming now, the 3D packaging that might give the impression that "better, cheaper, faster stuff every two years" will keep on existing few more years (until 2030?...).

I guess the next step is integrating the proc, the memory and the chipset under the same package via TSV, and that might elongate or gives some time to the new processes for being released. For example "proc @ 10 nm + memory@ 14 nm +chipset @ 20 nm" then  "proc @ 10 nm + memory@ 10 nm +chipset @ 20 nm" then  "proc @ 10 nm + memory@ 10 nm +chipset @ 14 nm" and so on...

seaEE
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Moore or Less?
seaEE   7/15/2014 12:33:56 AM
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Or maybe things will accelerate again once silicon is replaced.  Moore's law might apply to other processes as well, and all processes might have an asymptotic character to them as they approach their limit.

A Moore, more and more :)

http://www.youtube.com/watch?v=FeOxiBOmJOU

rick merritt
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Stake in the ground
rick merritt   7/14/2014 8:43:38 PM
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Meyerson reinforced what I heard at Semicon West last week -- that the 5nm node in about 2020 is probably the end of CMOS as we know it, assuming we can get over the sizable hurdles to get even to that point. After that, we need something new -- graphene, carbon nanotubes, quantum computing or who knows what to get to significantly higher levels of performance.

Of course existing processes will be used with clever designs for many, many years. Packaging advances also will drive performance increases. But the old curve we have been riding of better, cheaper, faster stuff every two years will be at an end.

It was fun, eh?

 



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