I see the graphs, thanks, but the only way there is any savings is if the added silicon is not as decent as the single crystal substrate (like cheap polysilicon not epitaxial). But then you're sacrificing performance, not really scaling down good performance.
Great comments @resistion and @alex_m1. As to cost savings, the footprint is 25% of the original and the total silicon area is 50% when folding a logic design into two layers. Why? Mostly repeaters/buffer savings and transistor sizes....average wire length in the chip goes down. This blog goes thru some of the details http://www.monolithic3d.com/3d-ic-edge1.html. And both layers are mono-crystalline silicon...with layer transfer the cost of the top layer mono-Si is amortized over the 10-20 times you use the donor wafer. Bottom line...it looks just like a node of scaling.
Yes, on the 2nd and subsequent layers, one gets SOI naturally in the monolithic process flow...cost savings and performance benefits. However, one has to deal with improving the heat conduction. Heat removal is a matter of getting a high enough lateral and vertical conduction to a sufficient heat-sink to overcome the operational heat generation. This blog talks to this with reference to an IEDM2012 paper by Stanford http://www.monolithic3d.com/blog/can-heat-be-removed-from-3d-ic-stacks on how to do that. Lateral is solved by rigorously using the Vss/Vdd network to move the heat laterally as if the 2nd layer 'substrate' is bulk Si, and the vertical conduction is taken care of by the high density of available vertical 'heat pipes' of monolithic 3D...10e6-10e8/cm2. BC
Thanks for the referred links. I suppose if you can eliminate a fraction of the line connections (replacing them with vias) with each stacking iteration, there can be some savings. This could explain the asymptotic behavior. But for the heat removal, in the case that the layer on the heat sink is generating heat, the boundary condition no longer favors heat removal.
@resistion: I am not sure I understood your comments, but I will try to comment below. Also, there will be lots more info at the upcoming IEEE S3S Conference. See you there.
Cost savings: Yup, any added degree of freedom will eventually approach an asymptote. But we have given designers /EDA another degree...lots to gain before the parabola starts winning. Also, why not mix layers? Two logic layers (for logic redundancy), then one or more memory (maybe NV), then two more logic. Cool on both sides if needed. Might be a trick to mitigate congestion and help heat.
Heat: The IEDM work ran both layers (substrate and monolithic 2nd layer) really hard and hot, and reasonable cooling was accomplished with the interlayer vias and power grids. The larger issue was getting a big enough heat sink capability...had to go to liquid cooling to get all the watts out of the stack. But it's even worse for 2D, as there are more C and R power losses to overcome with the longer wires; hence, more power to accomplish the calculaton/task. And I can't imagine that we are going to be able to immerse our mobile systems in chilled mineral oil, as the Japanese did with their winning supercomputer. Rather, mobile/battery designs will be by lower Vcc, smart power usage, parallelism, etc....
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.