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DRAM based PCIe card
christopher_george   8/1/2014 1:12:40 PM
"What I don't think we have seen yet is a DRAM card plugging into the PCIe bus."

Actually this has been shipping by DDRdrive LLC since 2006, the DDRdrive X1 is a DRAM based PCIe card with an equal capacity of on-board NAND and a SuperCap PowerPack to provide the back-up power after a host power loss.


The market opportunities for DRAM based PCIe are obviously not as broad as Flash based PCIe today, but the inherent random write limitations of Flash relative to DRAM has yet to be overcome.  For those capacity constrained applications bound by random write IOPS, such as the ZFS Intent Log (ZIL), a DRAM based PCIe solution is a perfect match.

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Re: Interesting topics
wilber_xbox   7/31/2014 2:39:36 PM
Memory storage density are pushing the technology boundary because the price is such a delicate tipping point that companies can save millions on a small price difference. The explosion of the data storage and devices has and will spur the demand.

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Re: Interesting topics
elctrnx_lyf   7/31/2014 1:05:40 PM
Memory storage systems will play a much bigger role in the future consumer electronic products. The miniaturisation of flash will provide a chance for innovative and small electronic devices.

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DRAM on PCIe???
DougInRB   7/31/2014 12:57:18 PM
"What I don't think we have seen yet is a DRAM card plugging into the PCIe bus. That could change after the smoke clears next week."


Was this intended to be a joke?  If so, a smiley would have helped.  If not, please enlighten me as to why in the world anyone would want such a device?

In any case, the Summit appears to be chock full of interesting sessions.


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Interesting topics
resistion   7/31/2014 11:15:39 AM
I would look forward to a realistic cost assessment of 3D memories, with vertical NAND being the prime example, particularly how much area is added that is NOT stacked. Apparently, that was a big deal observation for Samsung's second generation V-NAND when it released its SSD based on it.

Regarding silicon proof of new memory technology, again it should be assessed whether Mb-scale silicon should be sufficient, since that costs much less (1000x less) than Gb-scale.

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New Flash Architectures at Flash Memory Summit
bberg950   7/31/2014 10:20:41 AM
My Architecture session (B-11/B-12)all day on Tuesday at this conference will include a SanDisk talk on "Data Shaping" for sub-20nm NAND, NVM Express (based on PCIe) talks from LSI/Avago and Fastor Systems, and a talk by FMS 2013 Best of Show winner NVMdurance on their patented endurance techniques.  At Tutorial T-4 on Wednesday: learn about M.2, an easy way to bypass SATA by connecting directly to PCIe.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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