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rick merritt
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Leveraging the flash controller
rick merritt   8/6/2014 2:33:23 PM
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I'd like to hear wha folks think about the smart flash initiative Samsung is driving at SNIA, NVMe, etc.

Can we access the many flash controllers in a data center to do other jobs or will this be a mess that goes no where...or?

resistion
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No more density expectations
resistion   8/6/2014 10:23:25 PM
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Whether direct shrinking, more bits per cell, or more vertical layers, the complexity and associated cost is countering the normally expected decrease of cost per bit. The bit quality is degraded. So of course, managing so many bits in one place would place a lot of demand on the controller. The controller cost should therefore be considered in the system cost to be fair. Then flash won't look so cheap anymore.

sw guy
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Re: No more density expectations
sw guy   8/7/2014 7:05:58 AM
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Could be, at least partialy, compensated by the fact that controller is until now poised to take full benefit of shrinkage.

Nevertheless, I too have the feeling flash is the only sector I know where manufacters are proud to annouce new *less* reliable product.

resistion
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Re: No more density expectations
resistion   8/7/2014 9:19:10 AM
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Agreed. Controllers are one or two generations away from 28 nm. The more demands, the faster they'll get there.

krisi
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Re: No more density expectations
krisi   8/7/2014 9:45:09 AM
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are controllers really that advanced in manucturing? one generation away from 28nm...I would think 65nm or 90nm would be more than sufficient for any controller, how many gates do you need?

resistion
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Re: No more density expectations
resistion   8/7/2014 9:50:07 AM
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Hi Kris, one controller I checked(http://www.tomshardware.com/reviews/jmicron-jmf667h-ssd-benchmark,3834.html) is made with 55nm, the only reason why further scaling came up is previous post sw guy noted that controller scaling is one way to address slowdown of cost reduction from need for more advanced controllers.

krisi
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Re: No more density expectations
krisi   8/7/2014 10:19:50 AM
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thank you @resistion...I just thought that few millions gates would be sufficient for the controller implementation so there is no need to go down to 28nm

TanjB
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Re: No more density expectations
TanjB   8/8/2014 9:29:30 PM
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@resition That is an unusually through review, quite interesting.

SSD controllers have a history of being stripped down to basics.  A couple of years ago they were typically an ARC processor, stepped up to ARM these days.  The ECC is a major IP block but it probably is more a problem of having rights to a competent design than it is a large number of gates.

In the PCIe era we are going to see "ordinary" drives in the 1TB range have thruputs in the 1.5 to 2.0 GB/s range, about 3x faster than SATA-3.  The NVMe command set is inherently efficient to handle, but still the controller will need to track the sector mappings, plan block erases in advance, infer sequentiality in user patterns, monitor wear levelling, as well as move data.  So we might see some pressure to move to the 28..35 nm range, probably an LP process, in the next wave of controllers.  Especially as the flood gates seem to have opened for 28nm capacity and new chips seem to come out every day.  With more mature design pipeline and less cost/delay on production it won't be long.

I wonder what Novachips is using for the HLSSD controller?  That seems pretty fancy.

 



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