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resistion
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Re: Intel's eDRAM
resistion   8/8/2014 1:00:17 PM
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I know they were starting to use 8T SRAM, that was a sign of problems for 6T. I assume the refresh controller will only refresh cells containing data. These could be sparse.

Violoncelles
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on chip eDRAM at IBM
Violoncelles   8/8/2014 3:03:24 AM
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IBM has been using on chip eDRAM on its chips for more than a decade .

resistion
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Re: Intel's eDRAM
resistion   8/8/2014 2:23:41 AM
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IIRC, refresh rate is lower for eDRAM, but not 0.

TanjB
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Re: Intel's eDRAM
TanjB   8/8/2014 1:42:32 AM
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Refresh seems to consume about 0.5W.  The L4 latency is about half that of DDR channels, and the bandwidth about the same as 4 DDR4.  Typical hit rate 95% (that would be remarkably good in general, but maybe the gamer market is what they aim at where locality might be better).

Not clear this is better than a Memory Cube.  But probably much cheaper.

xys
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Re: Intel's eDRAM
xys   8/8/2014 12:09:49 AM
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What is differenceof performance between Intel's L4 cache with eDRAM and regular DDR SDRAM on motherboard?

--

xys

resistion
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Re: Intel's eDRAM
resistion   8/7/2014 8:05:34 PM
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The DRAM will leak charge without a refresh, which requires power frequently every second. SRAM doesn't. Maybe SRAM doesn't sleep well enough anymore to conserve standby continuous power? What happened to near-threshold operation?

Susan Rambo
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Re: Intel's eDRAM
Susan Rambo   8/7/2014 7:34:27 PM
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Interesting. The article only mentions "The eDRAM also required 1/5 of the keep-alive power compared with an SRAM device." Could you explain more about eDRAM's constant refresh and is that something that would be fixed someday, do you think?

resistion
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Re: Intel's eDRAM
resistion   8/7/2014 6:43:41 PM
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Power saving is limited by constant refresh of eDRAM.

Susan Rambo
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Blogger
Intel's eDRAM
Susan Rambo   8/7/2014 6:32:48 PM
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I'm curious to know what engineers' opinions are of the eDRAM. Techinsights has an interesting analysis of the technology here.

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