Breaking News
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
User Rank
Re: SRAM size
GroovyGeek   8/12/2014 3:35:35 AM
Yes head to head comparisons are tough, but in this case Intel is not showing a PowerPoint but an actual product. TSMC will not ship anything they define as 14nm for at least a year, and in volume even later. Historically their SHIPPING SRAM sizes have been 10-20% larger than what has been advertised in papers, probably to meet SNM and other requirements.

User Rank
Re: SRAM size
buprestid   8/12/2014 3:21:26 AM
For these process parameters is there anyway to compare actual numbers? Just some conference papers and some slides here and there.

Intel comes out with the Gate Pitch x Metal Pitch in November 2013 that says they are much better.

TSMC rebuts that claim saying they are equal density at 16nm node.

Intel reiterates again from the chart here they have a denser far cheaper process.

User Rank
alex_m1   8/11/2014 11:12:35 PM
I wonder how can Intel reduce transistor costs while the rest of the industry cannot ? what's different ?

User Rank
Re: SRAM size
GroovyGeek   8/11/2014 9:37:14 PM
Buprestid You do realize you are comparing a shipping product to a conference paper presentation. Real SRAM cell sizes are substantially larger than what is advertised at conferences. I guess in a few years wwhen they get aroundto sshipping 14nm we will know.

rick merritt
User Rank
Re: Moore's law
rick merritt   8/11/2014 9:34:26 PM
@3D Guy: As Moore himeself said, before scaling stops it will slow down


User Rank
scalable to 10 nm
resistion   8/11/2014 9:03:39 PM
The same SADP techniques can scale to 10 nm, but tighter gate scaling looks dangerous.

User Rank
SRAM size
buprestid   8/11/2014 8:21:08 PM
Not bad for the SRAM size.

Intel : 0.0588 sq. um

Samsung : 0.064 sq. um ISSCC 2014

TSMC : 0.07 sq. um IEDM 2013


3D Guy
User Rank
Moore's law
3D Guy   8/11/2014 6:22:27 PM
Congratulations to the Intel team on a phenomenal engineering achievement. Keeping the cost per transistor going down by doing higher aspect ratio fins, boosting drive current and lowering transistor area needed is great.

I wonder, though, whether Intel can really boast that Moore's Law is alive and well... the yield challenge of high aspect ratio fins cost a year of delays (thereby the cost per transistor went down by 2x after 3 years instead of 2)... it also caused loss of face for Intel with major customers like Apple. 

<<   <   Page 2 / 2 Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)

What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.

Brought to you by:

Like Us on Facebook
Special Video Section
The LTC2380-24 is a versatile 24-bit SAR ADC that combines ...
In this short video we show an LED light demo to ...
Wireless Power enables applications where it is difficult ...
LEDs are being used in current luxury model automotive ...
With design sizes expected to increase by 5X through 2020, ...
Linear Technology’s LT8330 and LT8331, two Low Quiescent ...
The quality and reliability of Mill-Max's two-piece ...
LED lighting is an important feature in today’s and future ...
The LT8602 has two high voltage buck regulators with an ...
Silego Technology’s highly versatile Mixed-signal GreenPAK ...
The quality and reliability of Mill-Max's two-piece ...
Why the multicopter? It has every thing in it. 58 of ...
Security is important in all parts of the IoT chain, ...
Infineon explains their philosophy and why the multicopter ...
The LTC4282 Hot SwapTM controller allows a board to be ...
This video highlights the Zynq® UltraScale+™ MPSoC, and sho...
Homeowners may soon be able to store the energy generated ...
The LTC®6363 is a low power, low noise, fully differential ...
See the Virtex® UltraScale+™ FPGA with 32.75G backplane ...
Vincent Ching, applications engineer at Avago Technologies, ...