Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
GroovyGeek
User Rank
CEO
Re: SRAM size
GroovyGeek   8/12/2014 3:35:35 AM
Yes head to head comparisons are tough, but in this case Intel is not showing a PowerPoint but an actual product. TSMC will not ship anything they define as 14nm for at least a year, and in volume even later. Historically their SHIPPING SRAM sizes have been 10-20% larger than what has been advertised in papers, probably to meet SNM and other requirements.

buprestid
User Rank
Freelancer
Re: SRAM size
buprestid   8/12/2014 3:21:26 AM
NO RATINGS
For these process parameters is there anyway to compare actual numbers? Just some conference papers and some slides here and there.


Intel comes out with the Gate Pitch x Metal Pitch in November 2013 that says they are much better.

TSMC rebuts that claim saying they are equal density at 16nm node.

Intel reiterates again from the chart here they have a denser far cheaper process.

alex_m1
User Rank
CEO
cost
alex_m1   8/11/2014 11:12:35 PM
NO RATINGS
I wonder how can Intel reduce transistor costs while the rest of the industry cannot ? what's different ?

GroovyGeek
User Rank
CEO
Re: SRAM size
GroovyGeek   8/11/2014 9:37:14 PM
Buprestid You do realize you are comparing a shipping product to a conference paper presentation. Real SRAM cell sizes are substantially larger than what is advertised at conferences. I guess in a few years wwhen they get aroundto sshipping 14nm we will know.

rick merritt
User Rank
Author
Re: Moore's law
rick merritt   8/11/2014 9:34:26 PM
@3D Guy: As Moore himeself said, before scaling stops it will slow down

 

resistion
User Rank
CEO
scalable to 10 nm
resistion   8/11/2014 9:03:39 PM
NO RATINGS
The same SADP techniques can scale to 10 nm, but tighter gate scaling looks dangerous.

buprestid
User Rank
Freelancer
SRAM size
buprestid   8/11/2014 8:21:08 PM
Not bad for the SRAM size.

Intel : 0.0588 sq. um

Samsung : 0.064 sq. um ISSCC 2014

TSMC : 0.07 sq. um IEDM 2013

 

3D Guy
User Rank
Manager
Moore's law
3D Guy   8/11/2014 6:22:27 PM
NO RATINGS
Congratulations to the Intel team on a phenomenal engineering achievement. Keeping the cost per transistor going down by doing higher aspect ratio fins, boosting drive current and lowering transistor area needed is great.

I wonder, though, whether Intel can really boast that Moore's Law is alive and well... the yield challenge of high aspect ratio fins cost a year of delays (thereby the cost per transistor went down by 2x after 3 years instead of 2)... it also caused loss of face for Intel with major customers like Apple. 

<<   <   Page 2 / 2


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Dr. Duino Diagnostic Shield Deduces Dilemmas in Arduino Shield Stacks
Max Maxfield
13 comments
As you are probably aware, I'm spending a lot of my free time creating Arduino-based projects, such as my Inamorata Prognostication Engine, my BADASS Display, and my Vetinari Clock.

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)