Congratulations to the Intel team on a phenomenal engineering achievement. Keeping the cost per transistor going down by doing higher aspect ratio fins, boosting drive current and lowering transistor area needed is great.
I wonder, though, whether Intel can really boast that Moore's Law is alive and well... the yield challenge of high aspect ratio fins cost a year of delays (thereby the cost per transistor went down by 2x after 3 years instead of 2)... it also caused loss of face for Intel with major customers like Apple.
Buprestid You do realize you are comparing a shipping product to a conference paper presentation. Real SRAM cell sizes are substantially larger than what is advertised at conferences. I guess in a few years wwhen they get aroundto sshipping 14nm we will know.
Yes head to head comparisons are tough, but in this case Intel is not showing a PowerPoint but an actual product. TSMC will not ship anything they define as 14nm for at least a year, and in volume even later. Historically their SHIPPING SRAM sizes have been 10-20% larger than what has been advertised in papers, probably to meet SNM and other requirements.
To be fair TSMC has never said they are equal density at 16nm node (they said will catch up at the 10nm node).
Asking to other engineers: TSMC and Samsung cells are 1T fin, Intel cell is 2T fins so the comparison is not fair.
Very likely both TSMC and Samsung will utilize a larger 2T cell for faster phone SOCs, still it is only a my idea. Sure the 1T cofiguaration is a limiting factor in abailable clock speed ad low power consumption.
We'll see Intel SOC process, it is unlikely an even smaller cell footprint for certain applications with 1T layout, like is happened on 22nm with the 1T 0.092um2 cell.
I don't know if it's that Intel uses SADP while foundries use LELE. SADP would restrict layouts strongly, which fits Intel's manufacturing style (they used to be a memory company). Another is they they staged their big technology transitions over many generations (45 nm high-k, 32 nm immersion, 22 nm FinFET, 14 nm double patterning). Instead of one big barrier at 2X nm.
A question that always comes up for me when I see Mark Bohr boasting about Intel's process technology load over TSMC:
Intel may show TSMC having higher gate pitch x metal pitch. But I think the true comparison would be cost per transistor. TSMC owns significantly cheaper fabs than Intel, thanks to much better government incentives than exist in Taiwan (vs. the US). My experience is that the cost difference can be ~30% or sometimes even more. I wonder if Intel really has a significant lead in cost per transistor?
@3D guy - Intel gets plenty of incentives from the state of Oregon, Ireland and Israel. Not so sure about Arizona and New Mexico, but I imagine there must be a big carrot to keep them in these 2 dry states where water is at a premium.
The technical achievements by Intel at 14nm are excellent. Achieving 0.53 area scaling compared to 22nm requires incredibly complex processing technology for control of fin height, pitch, and passivation coverage.
The next step of manufacturing 50K or 80K wafers per month with high yields and high reliability is another order of magnitude in complexity. Let us hope for the electronics industry that Intel will achieve its goal of reaching high volume production in Q1 or Q2/2015.
The other vendors of FIN-based products have similar challenges to Intel, and it is realistic to expect them to have a similar time line between when the process was initially stable to when high volume of cost competitive products that also have high reliability is achieved.
Intel's progress to date is an outstanding achievement by the company and its ecosystem partners.
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