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prousseau
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Re: Moore's law
prousseau   8/21/2014 6:47:20 PM
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I'm curious on your statement Intel use SADP, it this a fact they shared after the webcast, or your guess; I did not hear this in webcast.  SADP is not free

resistion
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Re: scalable to 10 nm
resistion   8/15/2014 10:59:33 PM
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Anyone can estimate from the SRAM picture that Lg is 24-27 nm at 14 nm node. It's already leveling off.

double-o-nothing
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Multiple patterning cheapest after all
double-o-nothing   8/13/2014 9:47:00 AM
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14 nm must have lots of double patterning and triple patterning, much more so than 22 nm. It must mean ASML and the analysts have overestimated the cost of the steps being repeated.

escher
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Re: Intel has a lead?
escher   8/12/2014 11:32:18 PM
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@3D guy - Intel gets plenty of incentives from the state of Oregon, Ireland and Israel. Not so sure about Arizona and New Mexico, but I imagine there must be a big carrot to keep them in these 2 dry states where water is at a premium.

resistion
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Re: cost
resistion   8/12/2014 9:12:29 PM
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It would be interesting to see implications for its foundry business. It may or may not translate directly.

Simon7382
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Re: cost
Simon7382   8/12/2014 8:29:52 PM
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Intell is better, that simple. They are ahead of the rest of the indostry by at least 2 generations.

HJ88
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Intel's Achievements
HJ88   8/12/2014 11:19:55 AM
The technical achievements by Intel at 14nm are excellent. Achieving 0.53 area scaling compared to 22nm requires incredibly complex processing technology for control of fin height, pitch, and passivation coverage.

The next step of manufacturing 50K or 80K wafers per month with high yields and high reliability is another order of magnitude in complexity. Let us hope for the electronics industry that Intel will achieve its goal of reaching high volume production in Q1 or Q2/2015.

The other vendors of FIN-based products have similar challenges to Intel, and it is realistic to expect them to have a similar time line between when the process was initially stable to when high volume of cost competitive products that also have high reliability is achieved.

Intel's progress to date is an outstanding achievement by the company and its ecosystem partners.

resistion
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Re: cost
resistion   8/12/2014 9:31:24 AM
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I don't know if it's that Intel uses SADP while foundries use LELE. SADP would restrict layouts strongly, which fits Intel's manufacturing style (they used to be a memory company). Another is they they staged their big technology transitions over many generations (45 nm high-k, 32 nm immersion, 22 nm FinFET, 14 nm double patterning). Instead of one big barrier at 2X nm.

Gondalf
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Re: SRAM size
Gondalf   8/12/2014 8:57:03 AM
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To be fair TSMC has never said they are equal density at 16nm node (they said will catch up at the 10nm node).

Edited.

Asking to other engineers: TSMC and Samsung cells are 1T fin, Intel cell is 2T fins so the comparison is not fair. 

Very likely both TSMC and Samsung will utilize a larger 2T cell for faster phone SOCs, still it is only a my idea. Sure the 1T cofiguaration is a limiting factor in abailable clock speed ad low power consumption.

We'll see Intel SOC process, it is unlikely an even smaller cell footprint for certain applications with 1T layout, like is happened on 22nm with the 1T 0.092um2 cell.

3D Guy
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Intel has a lead?
3D Guy   8/12/2014 8:44:26 AM
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A question that always comes up for me when I see Mark Bohr boasting about Intel's process technology load over TSMC:

Intel may show TSMC having higher gate pitch x metal pitch. But I think the true comparison would be cost per transistor. TSMC owns significantly cheaper fabs than Intel, thanks to much better government incentives than exist in Taiwan (vs. the US). My experience is that the cost difference can be ~30% or sometimes even more. I wonder if Intel really has a significant lead in cost per transistor?

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