Actually the smallest cell published so far is the "10nm" cell shown at VLSI earlier this year. With a gate pitch of 64nm, metal pitch of 48nm, and the same fin pitch of 42nm, it was a bit smaller at 0.053 um2.
Also, a fair comparison for Intel vs Intel would be the 0.108um2 cell in 22nm which had the same 2-fin NFET design that was shown here. The 0.092um2 cell had only one fin per transistor. The 2-fin cell here has a width of 420nm. A single-fin cell would had a width of (420-84 nm) and an area of roughly 0.047um2, which would put it at 0.51X compared to the corresponding 1-fin cell in 22nm. However, a single-fin SRAM would have poor charactersitics, because it does not have the right beta ratio (PD>PG>PU).
The new report from Intel detailing the long awaiting 14nm process shows an amazing transistor structure with 2 new features.
1. Higher fins 42 vs.34nm of 14 vs. 22nm nodes
2. Non tapered (vertical fins) which is quite deviation from the 22 nm process.
I'm not sure what will the competitors (Samsung, TSMC GF) are planning for their fins' shape. It will be very interesting to see.
However I have not seen any revelation with regards to the back end and especially with the interconnect section of the process (BEOL). Looks like the transistors are getting better and better but the BEOL is basically stays the same. In that case are we seeing diminished return? Or the solution will be to yet adding more metal layers, also what about first metal layers CD, how small narrow can we make them.
I'm curious to see how Intel responds to this article. From what Mr. Or-Bach says here, it looks like their announcements of SRAM cell size may not be consistent with each other. Intel keeps saying Moore's Law is alive and well, but is cost per transistor really scaling once every 2 years as it used to? Isn't there a 2.5-3 year gap between 22nm and 14nm? Looking forward to hearing Mark Bohr/Intel's response. Maybe EETimes can contact him for comment?