Front-end design kit which would include Verilog, .libs and foot print views such as LEF
Back-end design kit which would include Front-end views and GDSII and Spice netlist (which is indeed the source of the hard IP).
For most companies we will release only Front-end design kits whereby the customer can complete the entire design without the GDSII and when they are ready for tape-out they would merge the GDSII at the fab. We have done this successfully in the past and the fabs also support this program.
The advantege of this approcah is we can protect the IP for the specific fab and we can help the customer tape-out quicker as well.
Please do not hesitate to ask any further questions or contact me directly at Analog Bits
You wrote "for a majority of Chinese fablesses, Analog Bits' IPs will come as "design kits." The IPs will be physically integrated into a chip in a clean room at TSMC, explained Tirupattur. He regards this process as a firewall to protect their IPs."
Do you have any more information on this? I don't understand how a design kit will help protect IP.
We've covered extensively how those global IPs from ARM, Imagination and Ceva have helped China fabless.
Time to pay attention to what's going on with the mixed-signal IP world. The Analog Bits' executive see that Chinese fabless chip companies are no longer satisfied by using standard IPs that they can get almost free from TSMC or EDA companies.