Hi Robert . This is Pawan Bothra - APT Electronics ( P ) Ltd India . We are ODM for led drivers for Philips . In one of our 300W projects we are using interleaved PFC followed by interleaved PWM flyback converter . BOTH the stages use the same IC UCC28061 . I had used this with the anticipation that the BULK ELCO ( 450V ) at the o/p of the interleaving PFC stage will further be reduced by the virtue of interleaving in the next stage .
We have made prototypes and I am looking for some theroritical studies or will do some theoritical calculations where the ripple current of the said bulk elco can be calculated with variation of the duty cycles of both stages .
Further I am even thinking of using SG3524/3525 for the interleaving stages.
When the duty cycle is exactly 50% and the ramp slope going up and down is exactly the same the ripple cancels and aproaches zero!
minus the edge spikes, dead time, edge jitter...but these are an order of magnitude smaller problems than bulk ripple.
But power supplies don't operate at this point, but can be tailored for a specific sweet spot where a supply typically operates.
If your system can tolerate more ripple outside the sweet spot your done. If not, then something else needs to be done.
And ripple specs are worst case across the load range.
Perhaps a layered article that builds on this one can go into the benifits of N phase interleaving and how it helps and the deminishing returns of adding more than 3 or 4 interleaved sections provide.
Also some insight into how big or small a problem of variable ripple% is over load can be would be useful. Comparing 2 phase with 3 phase over load would be a great example to raise understanding.
Also how dynamic voltage scalling can buy some headroom for ripple issues, especially at low load to high load transition points where the extra voltage headroom has limited impact, as both ripple and ramp response determine brownout and overvoltage failure points, with and without dynamic proactive voltage scalling also has a lot of value toward cleaner and more efficient SMPS design.
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