I do not know whether it will be useful to go in this direction - integrating iii-iv with Si. Even taking photonics example, ultimately most of the companies had to found way to make photonics possible in Silicon rather than integrating already existing iii-iv material with Si.
Quantum confinement can help in solving a number of issues but will create others. I think one of them will be low overall current as the energy states will be quantized and electrons mobility will be very limited.
In addition to quantum confinment, whidh has its own problems as pointd out by wilbur_xbox, the researhers are also increasing the percentage of indium in the ternary material system which they claim increased electron mobility significantly. More to come.
wilber_xbox: Quantum confinement can help in solving a number of issues but will create others. I think one of them will be low overall current as the energy states will be quantized and electrons mobility will be very limited.
I'm not sure the authors would agree on those points, but I'm checking on them for you to get a detailed explanation.
I asked the author for the details on quantum confinement and this is how he explained it : "Yes energy states will be quantized leading to lower charge carrier concentration. However we clearly demonstrate in this work that the mobility (more accurately injection velocity) gained in moving to quantum confined structures with higher Indium percentage is significant enough to compensate for the lack of charge carriers, so that the product of charge and velocity (i.e. current) is higher overall.
The question however, is whether this advantage is still retained down to 7nm dimensions where quantum confinement is even stronger due to the extremely small fin widths."
While these are encouraging results, demonstrating higher performance transistors built in III-V materials is the smallest piece of the puzzle. Even co-integration of NFET and PFET, which most likely need different materials are relatively easy compared to real challenge. On any CMOS chip you need a range of devices (transistors and passives) with different voltage requirement. Your I/O devices need a bandgap considerably higher than InGaAs. The problem is not that you cannot put difefernt materials next to each other. The real challenge is how to process them with different thermal budget requirements. There is simply not enough time to put these mateials in manufacturing at 7nm.
You are absolutely right! Samsung is not aiming for the 7nm node--not enough time. The Penn State group is demonstrating the feasibility only of an n-type III-V FinFET at 7nm. If Samsung bites, then they will try to solve the other problems by the 5nm node.
>> I don't Samsung is thinking about optics, but rather the best materials to achieve the 5 nanometer node and beyond.
I think there are many things that must happen before these ideas can go to the market. It is not just the technology, it is actually taking them to production. I am very curious to know how the issues of quantum mechanics which Intel has been trying to figure out for years is solved here. This shows no winner can afford to celebrate because the industry is very intense and competitive.
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