Ummmm 3D interconnection could give "one" node stop just to help some companies about costs. Still nobody can avoid the shrink, it could be delayed for a couple of years but it is inevitabile. Moreover we don't know the exact impact on costs of design and its times. Another variable is "heat" and its removal, not all devices can be successfully designed on 3D interconnection, high power cpus for example are not well suited at all for this approach, but i have the suspect that even high perf. SOCs may have serious problems to keep their speed performance in tiny devices with the Tskin trick.
I would make a distinction, stating that not all companies will benefit of these new stop gap solutions.
Intel is most certainly having battles within, and the proof will be in the cost of goods sold. The jury is still out. Can they stay competitive with the ARM competitors, AND, now that they are moving into the foundry business, can they stay cost/performance/power competitive? Will their 'new' packaging approach really pan-out, especially with cost/yield??
Product, system and design engineers will choose the lowest cost route that will accomplish their objective. It is indeed a great time to be in the semi industry as there are now, will increasingly be, more route options. Much of IoT/IoE will use the follower processes and nodes, as it will be 'good enough performance' (for now at least) at ultra-low power and will be cheap. There will be fewer and fewer, but still some significant users, of whatever is the most advanced highest performing technology out there. Intel is one of those who is still pushing the envelope in the traditional, brute force way...dimensional scaling.
3DIC, specifically monolithic 3DIC, looks like the technology that bridges the performance needs, low power constraints, and the low cost. CEA Leti is starting to show good numbers, and mobile product QUALCOMM has committed to monolithic for its future. I wouldn't be surprised if we see other major silicon consumers such as Apple follow suit soon. Also, there are a lot of interesting 3DIC/SOI/low-Vt papers in the IEEE S3S Conference Preliminary Program. The technology support is upon us. It will be a must see.
Moreover, m3D looks like it will also enable new architectures and system ideas, whether pure silicon based or heterogeneous...certainly an attraction for the entrepreneurial and the VC community. It is indeed a great time to be in the semi industry. We will no longer be driven by one or two 'leading' silicon vendors.
In this blog we focused on the other 90% of the designs that already recognized the end of Moore's Law. Those designs that do not command $1B market have given up scaling as the NRE contribution to the device cost would eat away any cost reduction that might be achieved by dimension scaling.
The blog was also trying to point out the paradigm shift in the semiconductor eco system that is already taking place as is evident by the action of fab equipment, EDA and IP.
Which bring us to the first comment about 450 mm which been push out - Why 450mm Will Be Pushed-Back Even Further, and Intel closure of Fab 42 and supporting the push out of 450 mm is itself admission that things had changed.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.