AD, thanks. But don't be too impressed. I have the whold content of Microcontroller Central and of IoT World archived and it's in a form that is pretty easy to copy and paste without needing additional editing (it's been edited once). So it's mostly a matter of going through the motions.
If there are any other blogs anyone remembers from either site that seem like they would be a good fit here, just sing out. I'll get it ported over, although I may update it slightly if it needs it.
Antideluvian,Thanks for a very useful design idea. I am yet to read that fully, as unlike earlier, all the figures in the article pdf do not open in a 'contiguous article' fashion. I will save in a 'contiguous word' for convenience of reading. May be as HR softwares extract engineer's vital features from CVs, in future, manufacturers standardise datasheet organisation for a "CPU feature extractor tool" to yield "Designer's CPU data sheet".
I have so far not seen any manufacturer come out with a good matrix summary of what are going to be lost when some are used. Have you seen any such "Peripheral availability Matrix package wise" or peripheral Exclusivity Matrix" provided by any manufacturer so far? This matrix may have to be a three dimensional one as pins also enter as one dimension. What is the best way to represent this?
I did a design idea in EDN on this topic "Program "excelerates" microcomputer-I/O allocation". Unfortunately need to get to know your micro quite well to generate a worksheet like this, but at the end of it you will certainly be an expert- until the next time you choose to change processors! Rich will remember a blog I did on the subject on MCC, but that forum no longer exists- I will see if I can recycle it on MCU Designlines.
It's a challenge, no question. I think most vendors offer some kind of pin selection guide. This one from Altera is a tool that helps. The image does just what you suggest, provides three dimensions (color code is the third). http://www.altera.com/literature/hb/qts/qts_qii52013.pdf
But it's going to take some fiddling to get the right assignments to the right pins and not blocking the perihperals you need, regardless of the tools.
The chips I discussed in this piece are supposed to allow any peripheral to connect to any digitial IO chip, the implication being without blocking. So that should make the problem you describe a bit less troublesome.