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gah4
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Metastability, or not.
gah4   4/19/2017 3:12:47 PM
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Yes metastability is important when crossing clock domains, but more often the problem isn't metastability but race conditions.  If you have more than one signal, such as a count, crossing a clock domain, sometimes you get the value with some bits before and some after the clock transition.  

 

Metastability problems occur at higher clock frequencies, race conditions crossing clock domains at any frequency.  I would put this along with metastability, as both happen when crossing clock domains.   This is why Gray code counters are used with FIFOs.

 

-- glen

denis.lachapelle
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Pseudo Random Sequences and CRC stuff
denis.lachapelle   8/18/2016 4:15:09 PM
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PRBS: Pseudo random bit sequence can be very useful for generating bit stream that could be used for testing data path or generate quasi white noise. These same generators can be use to generate cyclic redundancy code and to verify CRC compliance of or received data packet.

denis lachapelle

www.sysacom.com

 

 

 

mosspp
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Re: What would you add to the list
mosspp   7/20/2016 10:21:01 PM
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Meeting timing will be easier if you:
  • Use no more clock frequencies than absolutely necessary. If you need a slower rate signal, use a clock enable running at that rate.
  • Don't cross clock domains unless absolutely necessary.


fpgaeng
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Re: What would you add to the list
fpgaeng   7/19/2016 12:47:01 PM
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if your design is not appropriate for a pipeline then don't put one in. no one is forcing you to do it.  I can't tell if your are being sincere or just trolling.

jwizard93
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Re: CORDIC vs LUT
jwizard93   7/19/2016 11:33:42 AM
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@Kevin Nielson thanks for the advice. I assumed the shape was the real kicker but wasn't sure I wanted to mess with accuracy until I knew for sure. That seems like a viable way to get the area down. It's important that whatever I do is recreatable to a similiar accuracy using the FANN C library, as that's what I use to train. Shouldn't be hard to spot the tanh portion and switch it to this same function. Just so my offline results more closely match the FPGA's / determine a good weight set. Much appreciated.

KarlS01
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Re: What would you add to the list
KarlS01   7/19/2016 10:48:31 AM
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What if the input is not fast enough to fill the pipe?

What if the output is not fast enouugh to use a new result every cycle?

stevehgl
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Small correction
stevehgl   7/19/2016 3:48:51 AM
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Probably a small point, but usually "ALU" means "arithmetic logic unit", not "algorithmic logic unit".

Kevin Neilson
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Re: CORDIC vs LUT
Kevin Neilson   7/18/2016 8:03:26 PM
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I would guess that for a perceptron you don't need high accuracy; it's more the shape of the curve that counts rather than it being an exact tanh value.  You might be able to have a small LUT and do a low-precision linear interpolation (aka 1st-order Taylor).  Tanh is fairly linear through the middle region so mabye you could use a constant multiplier for that region, which might be as simple as a bit shift.

fpgaeng
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Re: What would you add to the list
fpgaeng   7/18/2016 5:11:24 PM
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for some types of designs latency is not that important, but the thorughput is more

of a concern. Once the pipe is full, you get a new result every cycle.

 

KarlS01
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Re: What would you add to the list
KarlS01   7/18/2016 4:13:13 PM
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@fpgaeng:  How about the downside due to increased latency.  clock frequency is not the only parameter that determines the true performance. 

If clock frequency increases, but overall performance stays the same or decreases it is not a good trade-off.

Multi-cycle paths should also be considered.

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