The news comes the same day NXP announced it will use FD-SOI for multiple future processors. So far, a total of just 10,000 FD-SOI wafers/month are shipping from all fabs including Globalfoundries and STMicroelectronics, said Sam Wang, a chip analyst for Gartner.
I take this to mean all FD-SOI wafers worldwide coming out of Soitec including the GloFo 22.
TSMC made the point that you can easier migrate a 28nm design to 22ULP than to FD SOI.
Imagine that you have a design that uses power gating or clock gating to manage power consumption. Moving that to FD SOI and changing the power management to use back biasing, requires a complete re-design of the SoC.
It's also a niche area. NXP are using it for ultra low power micro controllers. I doubt anyone is going to use it for GPUs or smartphone SoCs.
The near futur will tell us whether TSMC is making the big mistake not to go to FD-SOI.
Of course , comparing the number of 28 nm bulk wafers with 28nm FD-SOI has no value since Samsung and ST are the only companies producing 28nm FD-SOI. The good reason why NXP is not ordering its FD-SOI 28nm wafers to GlobalFoundries is simply because GlobalFoundries started FD-SOI with 22 nm.
FS-SOI has this valuable feature for a back-bias for low consumption and a foward bias for high performance dynamically on the same chip that Bulk Si is missing
Would they proceed to 7+ without EUV. The node is a bunch of specs, EUV is just something they want to insert, but they really don't have as a 24x7 tool.
It looks like they are using 5nm information for their 7+, which seems premature. 7+ 1.2x density shouldn't have to change the number of immersion masks as they implied. For example, there is room to shrink CPP only. Changing MMP would be too disruptive. And for that 5nm design rule, EUV single patterning would not be sufficient anyway due to the line end gaps. On the other hand, the capacitance of cut SAQP grating lines (too many dummy) is not good for the Ps of PPA.