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resistion   3/16/2017 5:29:50 PM
Would they proceed to 7+ without EUV. The node is a bunch of specs, EUV is just something they want to insert, but they really don't have as a 24x7 tool.

It looks like they are using 5nm information for their 7+, which seems premature. 7+ 1.2x density shouldn't have to change the number of immersion masks as they indicated. And for that 5nm design rule, EUV single patterning would not be sufficient anyway due to the line end gaps. On the other hand, the capacitance of cut SAQP grating lines (too many dummy) is not good for the Ps of PPA.

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Oh boy, they poked the bear
emesdoublee   3/16/2017 2:35:36 PM
Looks like they poked the bear. The bear has bitten back.

22 nm planar process here you go. Bye Bye FD-SOI 22.

You see, the Soitec wafer is much more expensive. Can they even reliably supply those SOI wafers in high volume?

Just for a reality check

TSMC 28 nm = 167,000 wafers per month

FD-SOI = 10,000 wafers per month from all foundries! That's pitiful.

I absolutely love this quote:

"FD-SOI will always be the technology of the future,"

Good one!

Interesting to note that NXP is using Samsung and not the GloFo failure zone in any case.

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