I would be interested to see the scaling path for 3D XPoint.
The trouble with this version of 3D (as opposed to 3D-NAND) is that adding more layers adds more cost proportionally, so cost/bit saturates. The mature, higher-voltage underlying CMOS should be relatively cheap.
As I understand it is already at the same design rule as DRAM (and in fact NAND) ~20 nm. Whether it can scale lower, could depend on what factors could disturb the cells, e.g., thermal. Also the lines connecting the cells get more resistive, which hinders the reading.
MLC/TLC would be the best or most practical hope. But this requires a mature enough (resistive) memory, and this would also slow down the writing.
The retention is the key for any power savings to be realized. But it is not highlighted, which has me worried for this release..