Figure 1 - Synchronous design has a single master clock and a master set/rest driving all sequential elements in the design.

Figure 2a - Reducing clock insertion delay with a PLL - The delay nulling technique pictures here utilizes a phase-locked loop.

Figure 2b - PLL wave forms - The PLL adjusts the VCO to match the output clock to the reference point.

Figure 3 - Clock doubler circuit - The circuit is tricked into generating a clock which runs at twice the reference frequency.

Figure 4 - Clock doubler waveforms - The output waveform is phase-locked to the input clock, but runs at twice the input frequency.

Figure 5 - OC-12 DDR Transfer - High-speed serial transmission sends data at 622 Mbps along with a 311 MHz source synchronous clock.

Figure 6 - Phase-locked loop diagram - PLLs excel in frequency synthesis applications. Here the frequency is scaled by M/N.

Figure 7a - Delay-locked loop block diagram - The DLL adjusts its delay line to add enough delay such that the total delay exactly equals one or more clock cycles.

Figure 7b1 - DLL wave forms - The output of the clock buffer is delay by exactly one or more clock cycles