LOS ANGELES -- Reversible logic has been studied at a theoretical level for decades as an interesting counterpoint to conventional digital logic. But lately, circuit designers have been finding powerful energy-saving designs by adhering to the principle that information should not be discarded when it is processed.

One striking energy-saving example is a design approach that uses resonant charging of the capacitors in CMOS chips to conserve electrical energy. On every clock tick within a conventional circuit, charge is transferred from power to ground, and is therefore lost. A fundamental shift has been implemented in a logic scheme at the University of Southern California that uses the power supply as the clock and simply swaps charge between signal lines. The new strategy has lowered power dissipation by a factor of 10, according to USC researcher Lars Svensson.

The power-saving approach demands a different strategy for implementing logic. In a conventional logic gate, several signal lines enter the gate, then the signals are processed and merged, and the output is transmitted on a single output line. Once processed, the inputs cannot be reconstructed from the output; information has been thrown away, and along with it some electrical energy. The circuits are therefore irreversible. Rather than merging a number of inputs into a single output, reversible logic circuits have the same number of outputs as inputs. The same amount of information that entered the gate is represented at the output in a transformed state. And rather than being thrown away, most of the electrical charge is also transmitted through the gate.

The USC group has taken the theory and used it to find a practical circuit design method that could save a lot a power with today's circuit technology. "Most of the power dissipation in conventional CMOS circuits is caused by repetitive charging and discharging of capacitive loads, which dissipates all the energy injected into it from the power supply," said Svensson.

Svensson explained that capacitors usually get charged and discharged in a data path whenever they change logic states, from 0 to 1 or from 1 to 0. At that point, a switch connects the capacitor to the power supply to charge it, or to the ground to discharge it. That energy can be more than cut in half, however, if the power supply smoothly ramped up from 0 to maximum voltage in synchronization with charging a capacitor. In the same way, discharging a capacitor to 0 could be accomplished with much less power if it was discharged, not to ground, but through a power rail that ramped down to 0 during the clock period. Additional power savings could be reaped if the charge from discharging gates could be recycled over to the gates that were charging--rather than "grounding out" discharges and always drawing "new" charge from the power supply for charging gates.

Resonant charging accomplishes three goals--ramping up, ramping down and recycling--with a two-phase synchronous clock that serves as the on-chip power supply and as the clock. Whenever gates need to charge, they draw from the ramping up phase of the power supply, whereas discharging gates supply current to the down phase of the power supply. Because the charge returned by the down phase is available to gates on the ramping up phase, power is

effectively transferred from discharging to charging gates--rather than being dissipated as heat--on each clock cycle.

Normal circuits dissipate energy as heat, in an amount determined by the capacitor's size and by the amount of the supply voltage. With resonant charging, on the other hand, the amount of dissipated energy depends on the shape of the power clock's resistance-capacitance curve. The equation implies that power dissipation will be reduced as a direct function of the resistance-capacitance constant, and inversely with the length of the power clock's period.

"With resonant charging, most of the capacitance energy is recovered from the capacitors and returned to the supply, in contrast with conventional circuits where all the capacitance energy is dissipated when the load is discharged," said Svensson.

A circuit designed by the USC team, called a "blip" circuit, has tested out the hypotheses regarding power savings from resonant charging. The blip circuit is designed to substitute a power clock for the two separate circuits used on chips today.

The power supply of the blip power clock uses only two off-chip inductors, in addition to conventional components. USC has tested the blip circuit with many conventional gates; those that work were designed for non-overlapping clock phases, researchers have found. In addition, resonant circuits are a natural for chip-wide clock busses, because almost all of a clock bus's load is capacitive. Thus, a resonant clock circuit can be retrofitted to lower a chip's clock-driver power requirements. The researchers have also found that data lines can be retrofitted with resonant charging drivers. The researchers found that power at the output driver can be almost totally recycled with boot-strapped signal drivers, which return energy to the power supply rather than dissipate it to ground.

Test chips fabricated by MOSIS showed that a 4-bit 0.85-micron process, running at 6 MHz, used 10 times less energy with the blip resonant-charging circuit than a normal regulated power supply and two-phase clock. At 20 MHz, the power savings was still four fold.

USC is now doing simulations of memory circuits that use blip power clocks, and simulations indicate that SRAMs using n-well technology can lower on-chip power dissipation by 56 percent to 84 percent when operating at 200 MHz using resonant charging. A 16-bit RISC chip that employs resonant circuits is under development.

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