SAN MATEO, calif. -- More details about Intel Corp.'s forthcoming 64-bit processor have come to light now that the company has obtained a U.S. patent for a processor with a RISC-like architecture--presumably Merced--that can accept multiple operating systems and application programs with mixed instruction sets.

But as Merced draws closer to reality, observers said Intel may have to reckon with potential challenges from an unopened treasure trove of alternative patents that describe ways for a processor to execute RISC and CISC instructions. Moreover, Intel could face a second wave of legal challenges from Digital Equipment Corp., which developed its own dual-mode processor in the 1980s.

When Intel and Hewlett-Packard Co. first announced their plan to jointly design a processor compatible with both X86 and PA-Intel patent provides a sneak peek into Merced RISC instructions, it was widely believed they would pursue a very-long-instruction-word (VLIW) architecture. Such a scheme would have enabled the chip to run large groupings of instructions in parallel.

Observers now say the patent, granted late last month, indicates that the processor may be more akin to a RISC device. Although the patent does not rule out parallel dispatch, it describes the RISC-like concept of using 32-bit instructions to encode single operations, according to Linley Gwennap, editor of Microprocessor Report (Sebastopol, Calif.).

"Merced will use some of the basic concepts of VLIW, but not the strict VLIW design done in the '80s," he said.

Gwennap noted, however, that it's still unclear whether Intel will actually put into practice the techniques described in the patent, which was filed in February 1995--about two years after Intel and Hewlett-Packard joined hands. Both Intel and HP refused to comment on the patent and its relationship to Merced. Analysts expect that processor will be introduced in 1999.

Others said Intel and HP would risk too much by going with a VLIW architecture. "It would have made sense to migrate to something that doesn't have as much baggage. VLIW brings that advantage," said Richard Belgard, a computer consultant in Cupertino, Calif. "But the major disadvantage of VLIW is that it requires brand-new compilers to get from source to object code. VLIW basically ties your object code to one machine."< P> Intel began heading down the path of using a RISC-like architecture starting with the Pentium Pro and, later, the Pentium II. "It would make sense that Merced could pick up on that class of technology," said Dean McCarron, principal at Mercury Research (Scottsdale, Ariz.). On the other hand, he said, Intel's VLIW-like MMX instruction set demonstrates that the company will draw from VLIW where it makes sense.

The patent describes how an application written in both X86 code and IA-64 code can execute on a single processor through the use of a mode bit to interpret incoming instructions. The implication, according to analysts, is that only those portions of the application software that can benefit from IA-64 need to be converted, a trick that should keep application code sizes from ballooning.

In many ways, the patent suggests that Intel will opt to gradually convert to IA-64 code in much the same way that Apple Computer Inc. migrated from the Motorola 68k to the PowerPC. "It should ease the transition from X86," Gwennap said.

For some analysts, the decision to move away from X86 in a gradual manner gives further credence to rumors that Intel is handling most of the Merced development work. This group maintains that HP defined the PA-RISC portion before the two companies officially said they would work together on Merced. Indeed, the patent was assigned only to Intel.

The patent does not specifically describe how Intel will implement the Merced chip. Instead, Intel describes at least five different methods of arranging the instruction cache, decoders and translator blocks before reaching the execution unit. "Either they want to confuse everybody or they have decided which one they'll choose," Belgard said. "This leaves them a lot of flexibility."

In each case, however, it's clear that there is a separate register file for RISC and CISC instruction units, Belgard noted. In most scenarios, Intel describes two register units flowing into a single execution unit. However, the company also leaves open the possibility of using two instruction caches that connect to separate decoders and execution units, with each execution unit having its own register file. In any case, it's strongly hinted that Merced will have a single integrated processor core, Gwennap said.

One of the claims in the patent also calls for a translator to convert CISC instructions to RISC inside the processor. That scheme leaves Intel the option of making a low-end processor that would enable software emulation, Belgard said, similar to how Digital uses a software layer to translate X86 instructions into Alpha native instructions.

Last year, Intel filed a similar patent application with the World Intellectual Property Organization. That application, which is still pending, attempts to make some broad claims over dual-mode processing.

But Belgard said the recently issued U.S. patent is much more narrowly focused and takes pains to distinguish itself from other dual-mode processors such as Digital's VAX, a processor made in the 1980s that accepted VAX code and its predecessor PDP-11 code.

Indeed, Intel isn't the only company to claim a technique to process X86 and RISC code in a single processor. At least three patents from Exponential Technology, which recently shut its doors after lackluster sales of its BiCMOS PowerPC chips, described ways to use shared registers between RISC and CISC instructions with separate instruction decoders. One patent in particular stands out: a way to emulate X86 segmentation in RISC using a paging unit and some extra hardware.

"The beauty is that Intel had done a weird segmentation and got a patent on it, and now here's a way where you don't have their hardware at all so you don't violate their patents," said a source close to Exponential who requested anonymity.

That could make the Exponential patents attractive to companies looking to challenge Merced. According to the source, Exponential is now trying to sell or license those patents, though the source said no deals have been made yet.

With the resurgent interest in X86 processors from startup companies such as Centaur, Transmeta and Rise Technology, there may be plenty of interest. "Some smaller vendors are looking for technology to give them an edge," said Mercury analyst McCarron.

Meanwhile, IBM Corp. and Motorola Inc. are preparing a 64-bit competitor of their own, code-named G4, that will put two to four CPUs and a cache inside a module.

Besides the impending competition, Intel may be inviting legal challenge to its patents. The dual-mode processor patent makes a distinction between its method of taking in two application programs using different instruction sets and that used by Digital's VAX processor. Unlike the Intel approach, the patent points out that the VAX could accept only one application and one operating system at a time, which meant that a new OS and applications had to be created. A Digital spokeswoman said the company would not comment on the patent or the case.

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