San Jose, Calif. -- The ASIC-signoff paradigm is under siege.

Observers say that a shift is in the offing that augurs dramatic changes in tools, methodologies, and ASIC and EDA business models--and that will require today's ASIC designers to acquire new skills.

ASIC signoff is the point at which designs are given to ASIC vendors for both implementa-tion and fabrication. These days, nearly all ASIC signoff takes place with gate-level net-lists, after synthesis and before layout. However, many industry watchers believe that, in the future, signoff will move up to the register-transfer level (RTL) and down to the physical design level. Million-gate devices are simply too complex to allow complete gate-level design.

At the same time, the physical demands of deep-submicron ICs are pushing some designers to do their own layout. With systems-on-silicon, different blocks in the same chip may be signed off at different levels, ranging from RTL to GDSII layout data.

Underlying the divergence in signoff is a blending of RTL synthesis and layout into a much more tightly integrated process. A technology and marketing battle is raging over whether synthesis will become a "back end" utility controlled by layout vendors or whether layout tools will become an adjunct to a new generation of smart synthesis offerings.

The potential implications of the signoff shift are staggering. ASIC-vendor business models that assume gate-level signoff are coming under challenge. The future of such EDA vendors as Synopsys, Cadence and Avant! hangs on the question of whether synthesis will reach down to absorb layout or vice versa. And new tools--including behavioral synthesis, design planning and RTL estimation--will soon become essential, mandating a massive educational shift among designers.

There are differing views on how extensively and how soon the ASIC-signoff paradigm will change. "RTL signoff is really another way of saying the ASIC vendor is engaging in design services," said analyst Ron Collett, president of Collett International (Santa Clara). "RTL signoff will become commonplace for designs that aren't performance-driven, but gate-level signoff will be with us for a long, long time."

But analyst Gary Smith at Dataquest Inc. (San Jose) believes "gate-level [signoff] is going away. You'll either do it at the register-transfer level or at the physical level. Even if you do it at the physical level, you're going to have to bring those results back to the RTL."

But a number of capabilities have to be in place for RTL signoff to happen, Smith said, and they probably won't be there until 2001. Those capabilities include RTL virtual prototyping, through design planning and estimation; physical verification; Virtual Socket Interface (VSI) alliance standards; a system-level design language; and a test methodology.

Avant! Corp. (Fremont, Calif.) believes gate-level signoff could become a thing of the past after 0.25-micron designs become commonplace in 1999, said engineering vice president Chi-Ping Hsu. "Either the front-end user will be doing more physical design or the ASIC vendor has to provide more services," he said.

Rich Goldman, director of the semiconductor vendor program at Synopsys Inc. (Mountain View, Calif.), expects to see a "spectrum" of signoff methodologies, from RTL to physical. "There will be a certain class of designs where the [gate-level] net-list will continue to make sense," he said.

Goldman said Synopsys prefers to think in terms of "RTL handoff," since the word "signoff" implies a level of guarantee that may not be possible for some time.

Rod Favaron, director of the advanced verification business unit at Mentor Graphics Corp. (Wilsonville, Ore.), observed that "RTL handoff is occurring today. It's done by consultants and people like that. RTL signoff we haven't seen yet."

Cadence Design Systems (San Jose) is preparing its customers for "deep-submicron signoff," said Jim Ensell, vice president of marketing for the deep-submicron business unit. A system chip might include blocks signed off at the RTL, gate-level or physical design levels, as well as soft or hard cores.

Major ASIC vendors are already engaging in RTL handoff with selected customers. But not everyone considers it the wave of the future. LSI Logic (Milpitas, Calif.) does some RTL handoff today but doesn't expect it to claim more than 5 percent to 10 percent of its overall business model, said John Gallagher, marketing manager for CAD methodology at LSI.

In fact, LSI Logic considers the interest in RTL or physical design signoff a "symptom" of the inadequacy of EDA tools for very deep-submicron design, Gallagher said. "Our focus is on improving tools and methods so people aren't forced into one of these solutions," he said.

NEC Electronics (Santa Clara) and Toshiba America Electronics Corp. (San Jose) said they are developing RTL signoff flows. Shorter term, such vendors are working with users who want to sign off using static timing analysis as opposed to gate-level logic simulation.

But James Wu, director of EDA at Toshiba, had a crisp warning. "Frankly speaking, today's tools have no very strong method to optimize the RTL that's been generated," he said. "Unless quality can be assured, if we interface with customers purely at the RT level, there's a risk we may not get a very good design."

ASIC and EDA vendors agree that RTL signoff won't work if designers think they can just throw RTL code over the wall. Designers will have to get reasonably accurate estimates of timing, power and area, and the requisite RTL estimation tools are in their infancy.

Much attention is being focused on RTL design planning--essentially a combination of floor planning and estimation. "RTL floor planning could be a possible solution, but there's no proof," said Wu. "The challenge is how close the estimation can come to the final result. If the correlation is ý50 percent, there's zero value."

"We don't believe estimation technology can be made robust enough to have a single-step RTL signoff," warned Cadence's Ensell. "There are going to be iterations through implementation from the signoff level."

Beyond estimation, said Mentor's Favaron, is the need to improve RTL verification. "Precharacterized" silicon processes and intellectual property will also be key.

ASIC designers who move to RTL signoff will thus have to learn new tools and methodologies for floor planning, estimation and verification. Their counterparts who delve into physical design face the even more daunting task of learning about IC placement, routing and physical verification.

"If you want the RTL user to do physical design, you have to automate the whole process," said Avant!'s Hsu. But even so, he acknowledged, those who go below RTL will have to have some knowledge of layout.

Vendors also feel the heat from the pending shifts in signoff methodologies. Suppose, for example, that Hsu is correct in saying that RTL synthesis and layout will have to become "almost like a single tool" and that they will need to be provided by the same vendor--presumably Avant!--if they are to work with very deep-submicron ICs. What does the future then hold for the likes of Synopsys?

"Clearly, it is a huge challenge for Synopsys," said Hsu. "They are struggling to find a way to get knowledge of physical design. From my point of view, it's easier to go from layout into the logical domain than the other way." He said that Avant! has some "advanced study" under way in deep-submicron synthesis and that it intends to provide a solution.

Both Ensell and Favaron said RTL synthesis will become a "back end" process that's less visible to the user. Ensell said Cadence views design planning as a "cockpit" that will invoke synthesis, which he said will become a "commodity type of thing."

Synopsys, needless to say, has a different point of view--one in which synthesis remains the centerpiece of RTL implementation but expands to include more physical design. "Back-end optimization will go on in synthesis, but synthesis won't become a back-end process," said Sanjiv Kaul, vice president of marketing for the design tools group.

Asked whether the blending of synthesis and layout is a threat or an opportunity for Synopsys, Kaul replied, "It's both. But we're excited about the changes in the marketplace and think we're well-positioned to take advantage of them."

If ASIC designers start signing off at the register-transfer level, one might assume they'll no longer need or buy RTL synthesis. Not so, according to Dataquest's Smith; some form of fast synthesis will still be necessary to get timing and power estimates.

RTL signoff opens the opportunity for ASIC vendors to do more design services. But if designers go all the way through layout, why not go to a "pure" fab like TSMC? "The fundamental difference is the level of guarantee," said LSI's Gallagher. "And if you're going to embed a complex core, it's probably going to have to come from the ASIC vendor."

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