SAN JOSE, Calif. -- Intel Corp.--while emphasizing that it will continue to drive forward the 32-bit Pentium architecture for years to come--introduced the IA64 instruction set architecture at the Microprocessor Forum here today. It further hinted at the hardware organization of the Merced chip that will be the first implementation of the architecutre.

IA64, according to the company, will rely on compilers to explicitly indicate the available parallelism in code. Explicitly Parallel Instruction Computing (EPIC) was the marketing term Intel coined for the concept.

The EPIC idea rests on a number of familiar ideas, all of which will be new to the Intel world. First, and most significant, EPIC requires compilers to pack instructions into 128-bit bundles. Each bundle includes three machine instructions and a template. The template is used to indicate dependencies between the instructions.

This format permits two particular techniques that Intel chose to describe today. First is Predication. In effect, each instruction is associated with a Boolean expression that follows the instruction through the pipeline. The expression determines whether the instruction results are retired to the register file or ignored when the instruction is completed.

The second technique is a form of aggressive speculation. By moving long-latency instructions, such as loads, up in the code, the processor can begin the load process before it knows whether it will actually need the data.

The combination of mulitple-instruction bundles, predication and speculation, according to Intel, will allow IA64 processors to avoid much of the time now lost to mispredicted branches, to find many more opportunities for parallel operation in a program, and to avoid stalling while waiting for memory in many situations.

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