Posted: 11:45 p.m., EST, 5/8/98

LAS VEGAS — Motorola's new Networking and Computer Systems Group chose the recent NetWorld+Interop to reveal the first major extension to the PowerPC instruction set — and the first major rift in the PowerPC architectural family.

The group described a set of 162 MMX-like single-instruction, multiple-data (SIMD) instructions, collectively called AltiVec, that will be part of the upcoming PowerPC G4 core that is scheduled to sample later this year.

But the G4-class part from IBM Microelectronics, shown at an Apple Computer conference earlier this year, does not support AltiVec. The difference raises profound questions about the divergence of Motorola and IBM, its partner in the Somerset design center and Apple Computer Inc.'s traditional second source on PowerPC processors.

"We have participated in the discussions about the [AltiVec] extensions," an IBM spokesman said, "but we made a business decision not to offer them. We believe our customers are better served by a rapid increase in clock frequency than by a more complex instruction set."

The split over the G4 generation of CPUs places Apple in a bind. If it exploits the AltiVec instructions — a decision Apple is expected to announce on Monday at its developers' conference in San Jose, Calif. — the Cupertino, Calif., computer maker will be aski ng software developers to deal with two different PowerPC instruction sets: with and without AltiVec. Such a move would end the full second-source relationship in which Apple has always held IBM and Motorola.

In most other respects, Motorola's and IBM's versions of G4 are similar. Both were designed in the joint Somerset facility. Both are pioneering devices driving their company's move to copper interconnect. Indeed, Motorola's G4 CPU is scheduled to be the first device to roll off the company's 0.22-micron (drawn) HiP5 copper-interconnect process, according to Will Swearingen, manager of the portfolio marketing PC division at Motorola's Semiconductor Products Sector. The part is scheduled to sample in the second half of the year and to reach production in early 1999. It is targeted at clock rates in excess of 300 MHz.

IBM, meanwhile, has already delivered to Apple engineering samples of its own G4-class chip, one of which Ap ple chief Steve Jobs demonstrated at 400 MHz. It too was built using a copper-interconnect process. IBM argues that by staying with the original, carefully streamlined PowerPC instruction set, it will be possible to increase the clock rate of the processor more quickly, which will make up for the utility of specialized but difficult-to-use instructions.

Motorola's desire to avoid a public confrontation over the question was telegraphed in the choice of venue for the AltiVec announcement — not the Apple Worldwide Developers Conference, but the NetWorld+Interop communications trade show. At N+I, the company positioned the AltiVec G4 not as a continuing part of Apple's processor road map, but as an attack on the emerging high-end DSP market. Motorola will pitch the chip for access multiplexers, basestation controllers and similar applications where it would compete against Texas Instruments Inc.'s 320C6X family, the Analog Devices Inc. Sharc processor and Lucent Microelectronics' 16000 DSP.

The device thus straddles Motorola's DSP and PowerPC families. "We no longer have DSP or Power PC divisions. The [Semiconductor Products] Sector is organized along vertical solutions now," said Phil Grove, director of market development in the Networking and Computer Systems Group.

Grove described fitting the new processor, which has been under development for two years, into Motorola's new solutions strategy. "Trying to make a trade-off between DSP and complex RISC is very difficult," Grove said, "and we tried to avoid making it a battle of architectures. But there are a lot more things you can do in extensible architectures with a multichannel RISC with vector instructions, than with DSP."

Grove said the AltiVec PowerPC would be used in applications that required high-bandwidth processing of multiple simultaneous data streams. Motorola sees the existing 24-bit Onyx DSP core being used in single-channel client applications such as cellular-phone codecs and analog modems.

While the ne w instructions look suspiciously like a response to similar sets from Sun Microsystems, Intel and MIPS, Sam Fuller, Motorola's manager of system architecture and product planning, said that AltiVec was in fact the result of a program to add high-bandwidth signal processing to the PowerPC architecture.

After evaluating both SIMD and very long instruction word (VLIW) schemes, Motorola concluded that SIMD was a better fit with its architecture and would make it easier to maintain software compatibility. "VLIW is difficult to program, and is a very different approach than the superscalar RISC PowerPC architecture," Fuller said. By permitting the superscalar CPU to dispatch both conventional PowerPC instructions and AltiVec instructions in the same cycle, Motorola can use the same hardware to compute operand addresses, load and store registers, and perform vector operations. "In effect, we've already solved the dispatch problem that VLIW attempted to solve," Fuller said.

The new instructions are ha ndled by an additional execution unit, using 128-bit-wide registers and data paths to perform multiple operations in parallel for 8-, 16- or 32-bit integer data or 32-bit floating-point data. The instructions in the new set are similar to those in the MIPS and Ultrasparc-II SIMD extensions, including arithmetic, logic and data reordering.

Ambitious implementation
Though akin to these earlier SIMD extensions, AltiVec may be the most ambitious implementation to date. Each AltiVec instruction specifies up to three source operands and one destination operand. The 162 new instructions are divided into four classes. There are the relatively conventional arithmetic operations that perform parallel computations on data in the private AltiVec 128-bit by 32-register register file. In addition, there are various non-arithmetic operations, including compare, shift and rotate, and some logical operations such as AND, OR, NOT, XOR, AND-NOT.

More unusual are arithmetic operations that allow for el ements within a register to be summed, with the result going into another register. These instructions can implement an efficient dot-product operation, for instance.

Perhaps the most powerful among these is the permute operation, reminiscent of the complex data-swizzling instructions in the architecture developed by MicroUnity (Sunnyvale, Calif.). The instruction can essentially perform an arbitrary reordering of the bytes, words or double words in a 128-bit register in one cycle, placing the result in another register. Such an operation could extract or replace the header of a communications packet in a single cycle, or slash the time required for the messy pixel reordering required by MPEG-2 decoding.

The combination of the AltiVec instruction extensions and the speed of better than 300 MHz targeted for CPU would make the Motorola chip among the most powerful signal-processing engines yet announced, according to the company. For example, Motorola claimed, a system that now needs up to 30 DS Ps could shrink to just two to three PowerPC devices.

But Fuller's claim that the part will be "the highest-performance DSP on the planet" is not likely to go unchallenged at Texas Instruments. The Dallas company has been brandishing its premier C6X DSP for some time now. Analysts said it's still unclear whether the PowerPC will have an advantage over the C6X, but some haven't ruled out the possibility.

"TI's floating-point version of VLIW on the C67 was supposed to be a preemptive strike against things like this," said Will Strauss, president of Forward Concepts (Tempe, Ariz.), a research firm. "This looks very good against the C67. It doesn't mean it wins against C67, but it can. The question is: will the tools be available?"

The tool issue is not a trivial one. Motorola said, without naming names, that it is working both internally and with third-party tool vendors to provide C, C++ and assembler tools that will support the new instructions.

But SIMD, like VLIW, has proved p articularly resistant to easy use. Motorola documents state that the goal of the first-generation tools is to make the AltiVec instructions explicitly available to programmers, not to infer the best use of the instructions and registers in existing code.

Positive spin
Motorola, of course, has considerable leverage for driving AltiVec into the communications infrastructure. But the architecture's future at Apple is a more open question.

Sources close to Apple suggested that the computer company planned to say very positive things about AltiVec at its developers' conference. Yet how Apple will resolve the differences between IBM and Motorola over the architecture — and how it will sell its independent software developers on the need to develop parts of their code for two quite dissimilar instruction sets — remains to be seen.

One analyst speculated that Apple would ultimately offer under separate sub-brands both systems with fast IBM PowerPC processors and Macs usi ng the Motorola AltiVec parts. What is yet to be determined is which

of the two would be the premium brand. "For all we know, a 450-MHz IBM part will outperform a 400-MHz Motorola part with multimedia extensions," said Richard Doherty of the Envisioneering Group (Seaford, N.Y.). "No one knows how these chips will perform yet."

At press time, Apple declined to answer whether it would adopt the Motorola technology. "Motorola's multimedia extensions for the PowerPC promise exciting options for us and Macintosh developers," said an Apple spokesman.

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