SAN JOSE, Calif. — Copper interconnects — the heavily hyped next-generation semiconductor technology that promises gigahertz speeds — are having profound, unintended consequences for manufacturing and design.

In the equipment arena, heavyweights are scurrying to embrace a new process that relies heavily on electroplating. Indeed, a scrappy startup based here — CuTek Research Inc., founded by an electrical engineer with ties to Advanced Micro Devices Inc. — appears well-positioned to capitalize on the copper craze.

But the consequences of replacing today's aluminum interconnects with lower-resistivity copper may be greatest in the engineering world. The use of copper interconnects on deep-submicron silicon could set up new constraints for chip designers.

"Copper is not necessarily a plug-and-play technology," said Tom Taylor, director of metallization marketing for equipment-maker Semitool Inc. (Kalispell, Mont.). "It involves a significant difference in architecture, layout and [on-chip] metal structures."

Another major challenge, according to industry experts, lies not so much in making the copper interconnect itself but rather in laying down two layers of metal — called the seed and barrier layers — which serve as a primer onto which the copper is subsequently plated.

"People are having quite a lot of problems with the barrier layers," said Risto Puhakkar, director of research at market analysts VLSI Research Inc. (San Jose, Calif.).

IBM's edge
The rash of changes being wrought by copper has kicked off a race in which everybody is jockeying for position right out of the starting gate and almost nobody — save IBM Corp., which is universally acknowledged as the technology leader — has a clear advantage. (IBM disclosed its dual-Damascene-copper process last fall.)

Handicappers put Motorola near the head of the pack as well. However, knowledgeable industry sources point to several other semiconductor companies pursuing intense — though quiet — investigations of copper. These include AMD, Texas Instruments and Intel Corp. in the United States and NEC Corp., Hitachi and Fujitsu in Japan. In Europe, SGS-Thomson Microelectronics is taking a leading role.

"Some of the companies that started their programs a little late are doing everything they can — trading resources against time — to catapult themselves ahead," said Semitool's Taylor. "We can also expect to see Taiwan make a serious effort to be a player. Taiwan has got perhaps the largest capital-equipment budget in the world to spend over the next few years for new capacity. That new capacity will all be cutting-edge stuff and that's where we can expect to see copper metallization employed first."

However, semiconductor makers rushing to take copper interconnects from the research lab into real-world production are facing a big practical issue. Namely, there isn't much field-tested fab equipment to deposit copper onto silicon.

At IBM, which is moving swiftly to outfit a fab in Burlington, Vt., the approach was to respin what was available. "We found a piece of equipment that had good potential and then worked with that vendor to adapt that equipment to our needs," said an IBM official. "The equipment does include our proprietary technology." Here, sources said, IBM has focused heavily on the critical barrier-layer processes.

With its self-reliant approach, IBM claims it has a six- to 12-month lead on everybody else. Moreover, the IBM official said, the company has licked process problems and is making "production-quality" chips on its pilot line in East Fishkill, N.Y., while it gears up its Burlington fab.

That's impressive, given persistent industry scuttlebutt about yield problems faced by almost every chip maker. (While many analysts believe yield is a serious challenge, several semiconductor experts said the problems were simply the normal growing pains of a new process.)

Clearly, the paucity of off-the-shelf production equipment for copper deposition affects other companies more than it does IBM. This hole in the market extends to industry giants Applied Materials Inc. and Novellus Systems Inc., neither of which now has a production system to lay down the copper interconnect. Applied said it has one in development that it hopes to ship by year's end; Novellus said it will demonstrate a copper-deposition system at Semicon West in July. Both vendors do market systems now that address the barrier and seed layers.

"Right now, Semitool has the only tool for copper electroplating," said VLSI Research's Puhakkar. Indeed, Semitool appears to be at the domestic forefront with its LT-210 system, which is a second-generation product. One Japanese company, EEJA, has also fielded a plating machine.

A paradox of the new process is that copper is no stranger to the fab. It has sophisticated application in packaging, where plating equipment has been used to apply copper or gold solder-bumps under the wafer. However, there's little experience laying down copper on silicon itself.

Unfortunately, depositing microscopic copper interconnects on an IC is a difficult trick. The big challenge comes from the so-called high-aspect-ratio presented by 0.25-micron-wide vias and holes on an IC, which can have depths as great as 1.0 micron. "The problem isn't just depositing copper," said Chiu Ting, an electrical engineer who co-founded CuTek Research last year after stints researching copper at Sematech and AMD. "The problem is depositing copper to completely fill-in the etched pattern in the dielectric. You want to deposit it without forming any voids or small cracks."

Ting, who spent 20 years doing semiconductor-process research at IBM and worked on multilevel metallization at Intel, has completed a beta version of just such a copper-plating system. "I plan to deliver a tool that's able to deposit copper and is able to fill in all of the etched pattern in the dielectric," he said.

Ting said his technology will be different from the plasma-vapor deposition systems that have been adapted for first-generation copper usage. He said that he will supply systems this fall to a number of semiconductor vendors for evaluation.

CuTek and Ting are being taken seriously. "You can't ignore CuTek," said a competitor who requested anonymity. "They have laudable experience with the demands of high-density interconnect. And they have good contacts. But starting from scratch on something that's going to be a core technology for high-volume manufacturing is going to be very difficult."

The competitor pointed to Ting's close ties with former employer AMD. For his part, Ting admitted he is engaged in a joint technology venture with AMD, though he declined to provide specifics. He said he has talked to all the major semiconductor vendors about his equipment. CuTek won't commence full production until it has firm orders, but the systems will be "considerably cheaper" than the $3 million to $5 million cost of standard PVD tools, Ting said, and will have a throughput of 40 to 60 wafers per hour.

While filling in the vias on an IC is a big challenge, there are other issues. Foremost among them is the fact that the use of copper interconnects may constrain certain elements of IC

design. "Up to now, designers have had the freedom to employ widely varying features at any given level of metal for the layout of, for example, bus lines and signal-transmission lines," Taylor said. "To truly realize the potential of [copper], designers are going to have to rethink the missions of each one of the metal levels that are employed. They may well be constrained to a very narrow range of metal width at any given metal level."

That is, instead of using different-sized vias or contacts at a given lithography level, those features will have to be kept to a consistent diameter. The approach — which is often pursued even on today's Ics — is intended to avoid pushing steppers beyond their resolution limits.

With copper, however, the procedure could become mandatory. That's because copper interconnects rely on a critical final step — metal polishing, rather than conventional subtractive-etching — to smooth out the features plated onto the chip. However, if different-sized features are present simultaneously, "dishing" can occur on the larger ones while the smaller features are being polished.

Production challenge
A more-immediate, more-significant challenge is finding a good way to put down the seed and barrier layers. The two layers play a critical role in Damascene copper-metallization technology.

The process of making an IC begins with a thick layer of dielectric material, such as silicon dioxide (SiO₂). Standard-issue photolithography is used and a pattern of transistors and conductors is etched into the dielectric layer. Then, a barrier layer — typically a few hundred angstroms of a refractory titanium, or tungsten-nitride — is applied. The barrier layer blocks the copper interconnect from diffusing into the silicon. Next, a very thin seed layer is put down by physical-vapor deposition. The material serves as a "primer" onto which the copper can be laid. Finally, the copper itself is deposited to fill in everything and create the interconnects.

At the very end, a chemical polish is performed to remove excess copper sitting on top of the chip's flat surface. That leaves a web of conductors inside the dielectric layer.

Since forming the barrier and seed layers is so tough, some companies are attempting to combine the process into a single step. IBM, for example, is said to be looking at this technique. Experts report there are wet-chemical processes that have the potential to cut a full step out of copper-interconnect manufacturing.