SAN JOSE, Calif. — Different X86 processor companies are taking different paths to integrating circuitry on the motherboard of a sub-$1,000 PC, and their divergent strategies are raising a number of design questions: Has the processor bus outlived its usefulness? Where should the graphics subsystem reside? Will it be cost effective to integrate L2 cache onto the processor?

Integrated Device Technology Inc. will announce today at the PC Tech Forum in San Jose, Calif. that it has teamed up with an undisclosed chip set company to integrate its third-generation WinChip core into a north bridge device that would be compatible south bridge devices from Intel Corp. Meanwhile, IBM Microelectronics said is seeking a new X86 core with a small die size and low-enough power to include in its ASIC library, and is also considering becoming a second source for STMicroelectronics' all-in-one ST PC device as it continues to offer low-cost stand-alone 6x86 processors. The moves come as Intel is trying to dominate the low-end PC market with its P6 Celeron processor and stripped-down chip sets.

These developments suggest that chip companies are now taking three distinct directions to integrating more functionality on fewer components for low-cost PCs. IDT's approach will abandon the Socket 7 system bus by combining a north bridge with an X86 core. Another strategy pursued by Intel, by some graphics chip companies and by chip set suppliers looks to combine the graphics engine with the north bridge while continuing to use a stand-alone processor. Still others such as National Semiconductor Corp. and STMicroelectroincs (formerly called SGS-Thomson Microelectronics) are planning to incorporate graphics, core logic and the processor into one device.

The 0.25-micron Winchip 2+NB device from Centaur Technology, which can reach speeds up to 300 MHz, will be available in the first quarter of 1999. The move to integrate an X86 core into the north bridge, according to the company, has three main advantages: it reduces the number of clocks for the processor to access memory; cuts component costs by combining two discrete devices into one BGA-packaged chip; and gives OEMs the flexibility to continue to choose their own graphics engine.

"The processor bus makes sense only to a processor manufacturer," said Glenn Henry, president of Centaur Technology (Austin, Texas), referring to Intel's attempt to shut out competition by keeping its P6 bus off-limits to rivals. "We think the P6 is not going to be successful in a $500 system."

There are, however, some potential disadvantages to integrating the CPU with the north bridge. That integration would require OEMs to use a new motherboard, for instance, although Henry said Centaur hopes to ease the transition by making the Winchip 2+NB resemble a north bridge chip with just seven more interrupt pins.

In addition, the move limits what can be integrated onto the die. To keep its chip's die size to a minimum, Centaur has dropped plans to include L2 cache on-chip. Instead, it will double the size of its L1 cache to a pair of 64-k caches, beginning with the Winchip 2+ chip set to debut later this year. Henry said the performance will equal that of a 256-k L2 cache with a 3-1-1-1 access time.

Centaur's move to shun the integration of L2 cache for its second- and third-generation devices runs counter to the plans of Intel and Advanced Micro Devices Inc., both of which plan to offer processors this year that integrate L2. IBM Microelectronics will also integrated L2 cache into one of its X86 processors designed by the Cyrix division of National Semiconductor Corp., an IBM spokeswoman said, which suggests that Cyrix has similar plans.

But Intel, AMD and to some extent IBM are still being conservative by integrating L2 and little else onto their X86 processors. Jill Kaplan, director of IBM's X86 marketing strategy, said it's too early to tell whether bolting more peripheral functions to the processor will win out over discrete processors. That hesitancy to integrate more functions runs counter to Cyrix's plan to combine all PC components, excluding DRAM, onto a single die by next year. The two companies have also taken different paths on marketing the 6x86 processor. IBM is shunning National's decision to change the device's name to M2 and to drop the "PR" speed rating in favor of conventional clock frequency.

Still, Kaplan said IBM and Cyrix are in a "tightly interwoven" relationship. IBM today announced PR300 and PR333 6x86 processors, and plans to offer at least two more speed grades — one later this year and one in early 1999. What's more, IBM will sell X86 processors based on Cyrix's next-generation Ceyenne processor in 1999.

Cyrix "wants to pursue the X86 systems-chip but not exclusively as we understand it," Kaplan said. "I definitely see a difference in our strategies, but if you look underneath you'll see one is an annuity versus a new business development."

Even so, IBM is hedging its bets. Kaplan confirmed that IBM has been in discussions with STMicroelectronics about manufacturing the ST PC, which combines I/O, graphics with a 486 core. "We've looked at the ST PC, and it's looking to be very feasible," she said. "We are now asking ourselves if it's the right time to put our stake in the ground. We're looking at all the technologies for when the time comes."

IBM is also looking to add X86 functionality to its core library for ASIC customers. Kaplan said the 6x86 is too big and too power-hungry to be integrated with other cores. STMicroelectronics, which also offers the 6x86 through an existing licensing and manufacturing arrangement with Cyrix, reached a similar conclusion and is now developing its own next-generation X86 core, which can be offered as a stand-alone processor and as a core for system-on-a-chip designs. Kaplan said IBM will likely license a core X86 from another party.

"We do need to have an X86 core in our library," she said. "We will look to see what's out there that is licensible. Developing it ourselves doesn't lend itself to being as quick to market as does licensing."

Centaur is similarly pursuing higher-performance and faster stand-alone devices, even as it plans to combine its X86 core with a chip set. The company is now sampling its second-generation Winchip processors, which is equipped with the AMD's 21 additional X86 instructions (dubbed 3DNow) and four new MMX instructions. Centaur also added a second pipe to decode, issue and execute two MMX instructions per clock cycle, and has replaced the floating-point unit with a fully pipelined unit, along with other minor improvements. Centaur's road map also calls for yet another architecture called the Winchip 3, which is slated to arrive in the second half of 1999. Henry said the device will have a 12-stage pipeline instead of the six-stage pipeline it uses today. The 12-stage pipeline will enable the company to double the frequency of its device and to improve its performance up to 80 percent.