SUNNYVALE, Calif. — One of the first commercial applications of reconfigurable computing may help shatter the IC-verification bottleneck, if EDA startup Axis Systems Inc. has its way. The company is ready to disclose its mission to provide a reconfigurable computing (RCC) engine that establishes a new category of EDA tool.

Axis' engine consists of several boards of FPGAs that sit inside a Sun workstation, accompanied by host simulation software. Compared with existing, gate-level emulation systems, the RCC scheme promises lower cost, ease of setup and use, greatly facilitated debugging and an ability to directly verify register-transfer-level (RTL) designs.

While not as speedy as emulation, the RCC engine is orders of magnitude faster than RTL simulation, with equivalent debugging capability. The real power, said Gary Smith, analyst at Dataquest Inc. (San Jose, Calif.), is that it's targeted at the design team rather than the verification team.

"Companies are trying to cut back on verification teams," Smith said. "They would like to see verification drop back to 10 to 20 percent of design resources. In some cases now it's four times the cost of the design team — it's gotten really crazy." Axis, said Smith, has breakthrough technology that is "absolutely the right way to go."

"We know for sure you'll be able to simulate more, or you can shrink the time," said Mike Tsai, president and chief executive officer of Axis. "I think we should save at least half of the verification time."

No stranger to EDA, Tsai was co-founder and chief executive officer of ArcSys, which is now Avant! Corp., also based in Sunnyvale. He was CEO of GWcom, a wireless telecom firm, before co-founding Axis with Steven Wang, former vice president of engineering for Precedence and chief financial officer for the Electronic Design Automation Companies (EDAC). Wang is Axis' vice president of marketing.

The young company employs about 20 and has more than $7 million in investment capital from customers, Tsai said.

Emulation market leader Quickturn Design Systems (San Jose) is rumored to be preparing a reconfigurable-computing product as well. "Quickturn has been actively working on using reconfigurable technology for several years to solve compute-intensive problems," said Naeem Zafar, vice president of worldwide marketing at Quickturn. Zafar declined to comment on specific product plans, but he said Quickturn is initially focusing on design verification, and is ultimately looking at applications for reconfigurable computing in other areas of EDA or "even beyond EDA."

While Axis' product announcement is scheduled in the second half of the year, the company is discussing the general concepts behind RCC. What makes it "reconfigurable" is a massively parallel architecture in which RTL and gate-level code is mapped into hundreds of thousands of computing elements. These elements, comprising Altera Flex 10K devices, serve as custom processors.

Communication between elements is done with a systolic array structure that allows data transfer between nearest neighbors. The engine is not dynamically reconfigured on the fly during verification, but each design is individually compiled into the processing elements that are most efficient for the design. For example, an "if" statement will result in a different kind of processing element from an "always" statement.

Not quite emulation
While Dataquest's Smith will include RCC as part of the emulation market, Axis insists it's a very different beast. Perhaps the foremost difference is that emulation systems directly verify gate-level designs only, whereas Axis' tool will take a full range of abstractions, with behavioral code simulated on the host workstation and both RTL and gate-level code mapped into the RCC engine.

Wang claimed the RCC engine will speed simulation by a factor of hundreds or thousands. Moreover, because it handles RTL code, it can be used much earlier in the design cycle than emulation — and debugging takes place at the RTL source level, in a familiar Verilog simulation environment.

"You can swap the simulation from RCC into software," Wang said. "You can run fast in RCC up to the point where an error occurs, and then debug in software where all nodes are visible." Axis provides a functional Verilog simulator that works with third-party waveform viewing and source-level debugging tools.

A key conceptual difference, Wang said, is that emulators provide free-running hardware with no way to control the clock. The RCC engine, in contrast, will run under software control at all times. Software and RCC hardware simulation are synchronized at every clock cycle.

The advantage of this scheme, aside from the ability to debug at the RTL source level, is that it avoids the setup-and-hold problems that emulators must resolve when designs are mapped into the hardware. But there are trade-offs. The RCC engine runs about 10 times slower than emulators, and it can't run in-circuit, meaning that users can't plug the target system into the engine.

"We don't feel we are competing with emulation," said Wang. "People buy emulation mostly to plug into the target system."

Axis also promises a much faster and easier setup than emulation, which comes in the form of a large standalone system. The PCI-based RCC engine consists of eight boards that fit inside a Sun Ultra-30 or Ultra-60 workstation; the first release will handle up to 1 million gates.

The high cost of emulation is also a deterrent, and Axis will have an advantage there, said Tsai. Pricing for the RCC engine isn't yet available, but Tsai said costs will be around 25 to 30 percent of what one would pay to emulate an equivalent number of gates.

Though the RCC engine is controlled by software simulation, it shouldn't be regarded as a simulation accelerator, said Wang. While accelerators are aimed at gate-level timing simulation, the RCC engine handles functional verification only.

The RCC engine comes with an event-driven, IEEE 1364-compliant Verilog simulator. It's similar to other commercial offerings, said Wang, except that it assumes gate delays are zero and doesn't simulate timing.

The Axis solution is not designed for ASIC-vendor signoff and as such will not replace conventional simulation. But, Tsai noted, 70 to 80 percent of verification time is spent doing functional simulation, and that's what Axis promises to slash.

"We can address all large designs," said Tsai. "We aim at anybody over 200,00 gates. Graphics in particular has a high need for speed." A majority of the beta sites, he said, are graphics companies.

While the RCC engine can be used very early during verification, its first target will probably be later-stage regression testing, said Tsai. At present, he noted, it's not atypical for designers to run overnight regression tests and then spend hours tracing down a problem. Axis' solution can reduce that time to minutes, he claimed.

Tsai has had first-hand experience with the verification problem. In 1995, when he became chief executive officer of GWCom, he was involved in the design of a two-way paging system. "It was a very complex system, and I realized that verification was a major bottleneck," he said. "So I started Axis based on my experience."

Axis' technology is home-grown. Its technical people include Sharon Lin, vice president of hardware, previously chief hardware architect at GWCom; Ren-Song Tsay, vice president of software, previously chief architect at Avant!; and Ping Tseng, director of simulation, an expert in parallel computation and the chief architect of Synopsys Inc.'s Cyclone cycle-based simulator. The company has five patents pending on its technology.

"We have a strong team for both software and hardware," said Tsai. "The software was designed from the ground up to work with the hardware. I think we are the only EDA company who can do the whole solution. Others focus on either software or hardware."

Axis will hold private demonstrations at next month's Design Automation Conference.