SANTA CLARA, Calif. — Intel Corp. said today it has pushed back the production schedule of its Merced processor to mid-2000 from 1999.

"We have reached a point in the development cycle where the product is really starting to take shape," said Stephen L. Smith, vice president and general manager, Intel's Santa Clara Processor Division. "At this point, we have more precise schedule and product data, which allows us to better understand the scope of the product development, and we have communicated the new schedule to customers and the industry."

An Intel spokeswoman said the postponement was initiated not by a manufacturing problem, but through a re-examination of the scope of the Merced project, which was more complex than Intel had expected.

"We had a very optimistic timeline originally," she said. "We felt in order to deliver a high-quality product, we needed to push the schedule out."

The device is a joint architectural project involving Intel and Hewlett-Packard Co., but Intel has done the lion's share of the nitty-gritty work on the processor, avoiding some of the design issues that have plagued earlier industry joint-design ventures.

Merced deploys the IA-64 architecture, described in part last fall at the Microprocessor Forum.

With IA-64, Intel graduates from its traditional CISC architecture and uses techniques from the VLIW (Very Long Instruction Word) tradition to come up with EPIC (explicitly parallel instruction computing). EPIC is similar to VLIW in that both allow the compiler to explicitly group instructions for parallel execution. This technique eliminates much of the dependency-checking and grouping logic that consumes an increasingly large portion of advanced RISC and x86 processors.

One concern about the IA-64 device, however, is that the architecture must be able to accommodate the past as well as the future: it has to execute x86 instructions, for a huge installed base of x86 applications, as well as the new instruction set. Recompilation will be needed, however, to achieve optimum performance on native IA-64 instructions.

The first IA-64 processor was expected to appear sometime in 1999 using 0.18-micron technology. Analysts at MicroDesign Resources (Sunnyvale, Calif.) expected it to operate at roughly 800 MHz and to deliver 50 SPECint95 and 100 SPECfp95 (base). In x86 mode, Merced could match the performance of a 500-MHz Pentium II, a mainstream processor in Intel's PC line in 1999, MDR has reported. The IA-64 chip is likely to be upwards of 300 mm2, however, making it expensive to manufacture.

Intel was expected to shift to 0.13-micron design rules in 2001 and then to a 0.10-micron process in 2004. Intel had planned to introduce in 2001 a second-generation IA-64 processor, dubbed by some Merced II, offering even greater levels of performance.

"The overall complexity of something like this is enormous," said Michael Slater, editor of the Microprocessor Report (Sebastopol, Calif.) "It's not clear what they know now that they didn't know a year ago. It sounds like they were too optimistic."

Slater said having to execute dual instruction sets is probably not the chief concern. "You do have an entirely new instruction set that pushes the boundaries of things that have been done. And it has to have intimate ties with the compiler to achieve correctness, much less optimization." On the other hand, he added, the processor is expected to be 25-30 million transistors, a huge physical undertaking as well.

The delay could throw a wrench into plans by HP and other workstation vendors allied with Intel to stick a long dagger in the heart of Unix workstation rivals. The Intel spokeswoman, however, said customers were being supportive.

"I would say HP and Silicon Graphics are the two (workstation vendors) most directly impacted," Slater said. "The positive benefits are to the Alpha/Digital/Compaq camp and to Sun Microsystems, who have another nine months to move up the performance curve.

The slip also gives Digital a chance to push its 600-MHz 21264 CPU down from quarter-micron design rules to 0.18-micron and stay in stride with Intel on the process side, Slater added.