BURLINGTON, VT. — IBM Microelectronics today announced a $100 million expansion of its ASIC capability, including the addtion of more than two dozen new cores, a bolstering of its mask-making operations and a head-to-head challenge to Texas Instruments Inc. in the digital signal processor market.

The expansion is intended to help customers address key applications areas and to smooth their march toward complex 5-million gate designs, some of which are already on the drawing board.

"System-level integration is happening faster than I would have expected," said Bruce Beers, director of ASIC products for IBM Microelectronics, based here.

A prominent part of IBM's announcement was a new circuit that clones TI's successful TMS320C54X DSP, a device that has found wide acceptance in the cellular phone and basestation markets. IBM has already secured a half-dozen design wins for the discrete version of the DSP, and plans to offer its functionality in a synthesizable core by the third quarter, Beers said.

"We're focused on an area of business most attractive — cell phones and handheld devices," Beers said. IBM said its clone device is fully compatible with TI's DSP. It was developed in house at IBM and has been validated with third-party test suites, Beers said.

The device will be migrated to newer process technologies. "We're committed to extensions and compatibility" with TI's C54X, Beers said. "We will attempt to stay right in the middle of that [market] sweet spot."

Coupled with the disclosure last week that Lucent Technologies and Motorola Semiconductor are allying to attack TI's grip on the $3 billion DSP market, IBM's announcement is sure to roil DSP market positions. TI is estimated to own 45 percent of the business today.

But IBM is also viewing the broader market outside of DSPs, as evidenced by the scope of today's announcement.

Twenty-six new cores, including a licensing of Mentor Graphics Corp.'s Inventra core library, have been ported to the company's 0.25-micron process. They include Ethernet media-access controllers, phase-locked loops, new twists on the PowerPC and DMA controllers.

In addition, the company is spending $40 million to build a new mask-making facility here to ease capacity tensions on masks and to retain its position on the leading edge of technology as more designs move into IBM's SA27 process with its copper interconnect capabilities.

To illustrate the speed with which customers are migrating to dense ASIC designs, Beers said IBM is engaged in 75 design projects that involve more than 1 million gates, with the largest involving 3.2 million gates. One customer is deploying a five-chip design in the SA27 copper process, with the largest chip holding a whopping 5.3 million gates, he said.

While Dataquest Inc. (San Jose, Calif.) forecasts the market's average ASIC design to comprise 1 million gates by 2001, IBM this year will probably handle 115 designs with an average of 1.2 to 1.3 million gates, Beers said.

Even so, methodology and tools still pose a problem. Place and route in the classic methodology is a big area of concern, he said. At the same time, the industry is moving into co-simulation and emulation at highly abstract levels.

"The playing field is constantly shifting, and it's moving very slowly," he said. "The formal verification tools break with large designs; place and route breaks with large designs. We have to change the whole way people can do designs."