HONOLULU — IBM Corp. and Motorola Inc., which unveiled their respective copper-interconnect processes at last December's International Electron Devices Meeting, surfed into the 1998 VLSI Technology Symposium here this week with fast SRAMs manufactured on those copper-enhanced processes.

In many respects, the separate papers presented here resembled a pair of synchronized swimmers: both companies used a dual-threshold-voltage approach to maximize performance in a six-transistor SRAM cell. The 6T SRAMs are more compatible with the logic processes at both companies.

Jill Slattery, a senior manufacturing engineer at IBM's fabrication facility in Burlington, Vt., said a PowerPC microprocessor made with copper interconnects already is ramping up at the Burlington logic fab. IBM got ahead because of a decision made several years ago to create a virtual company within Big Blue, bringing together researchers and process development engineers from East Fishkill, N.Y., with manufacturing engineers in Vermont.

With the kinks worked out of its dual Damascene copper process, IBM also is riding copper to a leadership position in the ASIC business. As many as a dozen ASIC designs with copper interconnects are being readied for fabrication at Burlington, and foundry customers such as Cyrix are crying out for copper capacity there.

At the VLSI meeting, Gary Bronner, an IBM project manager, described a project to use copper interconnects in a test-vehicle 64-Mbit DRAM. The project was started with an eye toward the eventual integration of embedded DRAM to a logic process, Bronner said, noting that the metal pitch of the IBM 64-Mbit DRAM closely matches the metallization of IBM's CMOS 7S process now in manufacturing at Burlington.

Motorola and IBM have similar strategies in part because they have jointly operated the Somerset design center at Austin, Texas, for PowerPC development. (The companies announced today that they would end their collaborative work at the center.) But Motorola will gradually adopt copper interconnects across its entire product line, including low-cost MCUs, because the dual Damascene approach is less expensive, and copper improves reliability by sharply reducing electromigration problems, said Craig Lage, manager of SRAM process technology development at Motorola's Semiconductor Products Sector (Austin).

The Motorola SRAM described at the symposium has the smallest cell size yet reported for a 4-Mbit SRAM. At 3.97 square microns, the small cell yields a device with a die size of 32.7 mm² — 20 percent smaller than a previous design using aluminum wiring.

Motorola used a 0.2-micron (0.15-micron Leff, metal 1 pitch of 0.65 micron) process that will be in volume manufacturing by the end of this year at its MOS 13 fab in Austin, which is in the same building as the development fab where the copper process work was done. Later, a more advanced version of the process will be ramped up at the Motorola-owned fab in Richmond, Va.

The small cell size derives from a self-aligned local interconnect, with a capped-gate poly. The peripheral circuits were designed for performance, and use a low threshold voltage (Vt) of 410 mV for the NFET and 460 in the PFET. A higher Vt was used in the memory-cell array: 950 mV in the P-channel and 700 mV in the N-channel.

The 1.8-V-operation SRAM can be configured for low-power, mobile applications by using three metal layers, or a version with more interconnect layers for high-performance or stand-alone SRAMs. Lage estimated that the design would result in a 500-Mhz synchronous SRAM design next year, after starting out in the 300- MHz range (sub-5 ns access time) late this year.

He declined to say whether Motorola planned to adapt the copper process to the Siemens-Motorola fab at White Oak, Va., where DRAMs and SRAMs are being manufactured.

Lisa Su, project manager at IBM's East Fishkill semiconductor research and development center, described an SRAM cell that was slightly larger than the cell described in the Motorola paper, but which is in manufacturing today using a 0.22-micron, 1.8-V process. The 6.8-square micron cell is in use on a 288-Kbit cache in a 400-Mhz PowerPC processor that measures about 40 sq. mm. A shrink cell measuring 5.4 sq. microns also has been developed that is fully working, she added.

Besides the copper interconnects, the process uses cobalt to silicide the transistors, a material that can be extended to future process generations, she said. The 3.5-nanometer (nm) gate dielectric was nitrided to reduce the boron penetration during the doping steps, and the N2O material is able to withstand a 350°C thermal cycle.

IBM designed the SRAM to use lower (250 mV) threshold voltages (Vt) in the critical paths, which improves the standby current considerably. The standard 330 mV Vt was designed for the cache array. A 12.7-picosecond delay for an unloaded inverter translates into 480-MHz performance.

"Much of our recent work has been in learning about yields, what we call the composite health of the line, by tracking 60 to 80 different metrics," Su said.

Whither Japan?
At the VLSI Technology Symposium here, and at next month's Semicon West, copper is continuing to hold the attention of much of the industry. Besides the IBM and Motorola papers — five in all — separate research work into copper was presented here by a team from Rockwell Semiconductor, Applied Materials, Semitool and Rodel Corp., as well as joint industry-university papers from a Motorola-Stanford team and a Hewlett-Packard-AMD-Stanford group.

A lack of papers about copper work from Japanese companies was noticeable, though NEC, Fujitsu, and Hitachi research managers said they are working to complete development work by next year.

The 18 VLSI Technology meetings held thus far — usually alternating between Hawaii and Kyoto, Japan — have been roughly equally represented by papers from Japan and the United States, with European and Asian companies represented less. NTT Corp. won the best-paper award at the 1989 VLSI Technology Symposium in Kyoto for early work with copper interconnects. However, no Japanese companies or universities came to the 1998 VLSI meeting with research work on copper.

Eiji Takeda, deputy general manager of the renowned central research laboratory of Hitachi Ltd., said, "U.S. companies got started with copper development ten years ago or more. In Japan, the serious work is about five years behind the U.S. schedule. For Hitachi, we expect to be ready some time next year, but I can't say exactly when."

Toshiba researcher Junichi Wada came about as close to copper as any Japanese researcher this week when he described a dual Damascene process in which a niobium barrier layer is sputtered into the metal lines, and then a reflow process is used to put down aluminum-metal interconnects.

"Since copper is not a mature process yet, we decided to work on a method to reduce the resistance of aluminum interconnects. And by using a double Damascene process, we can reduce manufacturing costs by eliminating several process steps" compared with the traditional subtractive-etch method used widely today, Wada said. Also, the niobium barrier layer is thin, leaving more room for the aluminum lines, and Wada said the combination results in excellent RC (resistance-capacitance) performance without the extra expense of copper.

Intel Corp. is likely to combine copper with a low-K dielectric material between the metal lines, making the two-step advance together in the 0.13-micron process generation now under development.

Though the full benefits of copper's improved RC performance are realized when combined with a low-K dielectric, companies such as IBM and Motorola have decided to take it one step at a time, integrating copper into a dual Damascene process flow, and waiting until the manufacturers of the dielectric materials improve their materials. Getting consistency from batch to batch in the new dielectrics has been a challenge that makes their adoption premature until the 0.15-micron or 0.13-micron generation is ready. (Intel will move from 0.18-micron — now being readied for manufacture — to a 0.13-micron process on 300-mm wafers.)

And while copper will always be copper, companies will use different low-K materials at various future process generations, Slattery said.

Sass Somekh, a senior manager at Applied Materials Corp., said many companies — not only those based in Japan — are sticking with aluminum for the time being, partly because the newer dual Damascene process with copper requires a newer, and more expensive, equipment set to put down the barrier layer — typically tantalum or tantalum nitride — than a copper-seed layer, and the electroplating of the copper fill.

"Copper is going to happen, but it is not going to be a wildfire," said Somekh.