SANTA CLARA, Calif. — Hidden amid the fanfare surrounding the launch last month of Intel Corp.'s powerful Xeon processor are a host of technical surprises that will pose new challenges for systems designers. As a result, even seasoned engineers will have to delve into some unfamiliar territory before they declare their latest workstations and servers ready for release to manufacturing.

"The Pentium II was designed for a maximum of two CPUs in a system, while Xeon was designed for a maximum of four, so you really have to step up some of the design constraints," explained Gary Thome, manager of design engineering for Compaq Computer Corp.'s workstation division. "The other thing is that Xeon has larger and faster caches, which can draw more current."

At workstation vendor In-tergraph Computer Systems (Huntsville, Ala.), Jerry Peterson, vice president of engineering, said, "We don't think designing with Xeon is tougher, but it's different."

The challenges — which involve a series of updated electrical and mechanical specs — stem directly from Intel's desire to enable Xeon to support four-way multiprocessing. That imperative required Intel's engineers to work extra hard to ensure the integrity of all signals traveling among Xeon processors and its core-logic chip set. In addition, Intel had to make certain that systems would have enough power to keep all the CPUs chugging along as well as ample cooling to stay within thermal limits.

Accordingly, Intel has publicly issued design guidelines explaining several key systems-related issues for Xeon. These include:

• A new bus technology, called AGTL+;

• More stringent power-distribution guidelines along with a new VRM 8.3 voltage-regulator spec;

• A new physical and electrical package, called Slot 2;

• A new systems-management bus inside the processor cartridge; and

• Tougher thermal (cooling) requirements.

Xeon, which was unveiled last month, marks an impressive updating of the basic Pentium II. The processor is the first to use Intel's Slot 2 package. It also includes beefed-up L2 cache, a 100-MHz processor bus and the ability to address multiple gigabytes of memory.

"There are some challenges that are a little more significant than designing with Slot 1 processors," explained Jim Russell, director of engineering at Intel's workstation products division in Dupont, Wash.

New terminations
Leading the list of Xeon technology upgrades that will affect systems designers is the new AGTL+ bus. AGTL+, which stands for Assisted Gunning Transceiver Logic, links the processor to the core-logic chip set. The bus replaces the GTL+ connection, which debuted in Pentium Pro and is also used in the standard Pentium II processor family.

Intel's Russell confirmed that AGTL+ was put in place so that Xeon could support four-way multiprocessing. "The Slot 2 electricals were designed for a four-way system," he explained. "That's a very difficult problem to solve and it required a lot of optimization in terms of the topology that's used and the terminations that are used."

Intel's just-released technical documentation hammers home this point. "The design of the external Pentium II processor bus enables Xeon to be multiprocessor-ready," the documentation notes. "To relax timing constraints on a bus that supports up to six loads, Xeon implements a synchronous, latched bus protocol that allows a full clock cycle for signal interpretation and generation. This protocol simplifies interconnect timing requirements and supports 100-MHz system designs using conventional interconnect technology."

In practice, what Intel came up with in AGTL+ is a bus that incorporates low-voltage-swing I/O buffers and terminations at both ends.

AGTL+ differs from the predecessor GTL+ technology used in Pentium II in that AGTL+ includes an active pMOS pull-up transistor to "assist" (hence the bus's name) the pull-up resistors during the first clock of a low-to-high voltage transition. In addition, the Xeon's Slot 2 cartridge contains internal 150-ohm pull-up resistors to provide termination at each bus load.

Such strict attention was devoted to ensuring that the correct terminating impedance is provided for several reasons. Foremost is so that signal shapes don't degrade and so that there's not a lot of ringing and crosstalk. Also key is enabling the CPUs to maintain their outputs at the required high logic level needed to drive multiple loads.

"Some of the challenges with that topology — four processors and a chip set — were not only getting the signal to settle out and maintain the signal integrity, but also to get the signals to switch fast enough," explained Intel's Russell.

"It's a real balancing act between beefing up the buf-fers to the point where they can actually drive those lines having dual terminations," Russell continued, "and avoiding problems arising from having such fast buffers."

Intel also had to ensure that a bus engineered and optimized for a four-processor implementation — that is, a high-end Xeon server — would also work in a two-CPU workstation.

To make that happen, Intel engineers spent weeks defining the topology of the AGTL+ bus, trying to understand the wiggle room they had within the allowable signal tolerances. For example, in a dual-processor implementation Intel tested, it put together a six-layer motherboard and found that the best design used three routing layers to distribute the bus signals.

For OEMs to be successful in taking AGTL+ into the real-world — via either workstations or servers — experience will be important.

"It's really no surprise that a Xeon with a 100-MHz system bus has new challenges as compared to a Pentium Pro with a 66-MHz bus," explained Compaq's Thome. "So we've developed a set of tools and methodologies and have really beefed them up over the past five or six years. As a result, we felt that we were well prepared to deal with the 100-MHz Xeon AGTL+ bus."

Those tools include Spice-like software to assess signal integrity. Also important is a crosstalk analysis tool, because the AGTL+ bus is generally considered to have poor noise immunity. "A third tool we use is a timing analyzer," explained Thome. "You need not only to make sure that the waveforms look clean, but also that they go from one chip to another in the allotted amount of timing, which is now 10 ns for the 100-MHz bus, as opposed to 15 ns for the 66-MHz bus."

Thome added that Compaq is relying on its engineers who have worked with the Pentium Pro and Pentium II buses in the past. "From a knowledge and expertise standpoint, they already knew the best practices and techniques to use," he said.

Regardless of whether such in-house expertise is available, OEMs seeking to build Xeon-based systems will probably do well to implement the bus layout rules Intel has formulated. These are set down in application notes such as AP-830, titled "Pentium II Xeon processor/Intel 450NX PCIset AGTL+ layout guidelines," available on Intel's Web site. The 450NX core-logic chip set is for use in Xeon server implementations, for example. Workstations will use other sets, such as the 440GX chip set.

The Intel guidelines include a rigid set of signal flight-time and crosstalk specs. Indeed, Intel strongly recommends that engineers run analog simulations of the company's AGTL+ bus designs. Along with out-of-spec problems, simulations can help catch routing errors.

In practical terms, knowledgeable sources said that OEMs who are absolutely certain they've implemented the topologies recommended in the application notes can probably forgo simulation and just do testing on the back end. However, if a design deviates at all from the recommended topologies, simulation is an absolute must.

As a longtime systems vendor, Compaq has years of experience putting together buses for different system configurations. "You really have to design the layout of your AGTL+ bus," explained Thome. "When I say design the layout, I mean do you do all the AGTL+ components in a star or in a 'tee' or daisy-chained together. There are a variety of different topologies you can select."

Thome added that different configurations may require different approaches. "If you're designing in a two-processor situation, the way you're going to hook up the nets may be a little bit different than the way you would design for a four-CPU situation," Thome said. "The point is, when you start, you have to pick where your end design goal is. Once you select a topology for two CPUs, it may not be appropriate for four CPUs. However, if you select one for four processors, you can make it work for two processors as well. What to do here is, if you don't plug a processor into a particular slot, then you plug a terminator card in. The terminator looks electrically similar to the processors."

Power possibilities
Bus layout isn't the only subject that demands attention when constructing Xeon-based systems. Power distribution and cooling are also burning issues.

"The physical format of Xeon is different," explained Intergraph's Peterson. "Xeon's Slot 2 is a much taller module than Slot 1 — it has different packaging constraints that have to be dealt with. In addition, when the processor modules are a couple of inches apart, you have to get airflow ducted in properly to cool them."

Part of the problem is physical. First, the mechanical engineers on the system design team will have to factor in sufficient mounting rigidity so that the processors won't separate from the motherboard or cause cracks.

Next, they'll have to figure out how to get the Slot 2 processors as close to the voltage-regulator modules (VRMs) as possible. Though this sounds simple, in a two- or four-processor configuration, it can be a tight fit because of the heft of the Slot 2 cartridge itself.

Still, component location is crucial in minimizing on-board inductance caused by the incredibly fast rise times demanded of Xeon's power supply.

In addition, explained Intel's Russell, "You've got pretty significant current transients occurring, so the noise generated can be significant."

The way Intel avoided potential problems on a two-processor Xeon motherboard designed by the company's workstation division was to use a six-layer board in which three layers were dedicated to signal routing and the other three layers were dedicated to voltage and ground. "We've actually got two voltage planes in order to make certain we've got enough copper between the socket and the VRM," Russell said.

The Xeon VRMs themselves must supply higher output current and faster ramps than previously. They also support remote sensing to improve voltage regulation.

For Xeon system designers, Intel has included one other new and notable feature inside the Slot 2 cartridge. This is a new system-management, or SM, bus that supports three features. These are read-only memory containing information specific to the CPU in use; readable/writable and write-protectable memory that can be used for a manufacturer's system information; and a thermal-sensing device. The last thing is a readable digital signal that supplies highly accurate thermal data about the processor.

"For mission-critical applications, primarily in servers but also in some workstations, it's useful to instrument the processor for temperature and voltage," noted Intel's Russell. "If you've got a fan in the system that stops working and the temperature on the processor starts to get out of spec, you can be alerted to that through the SM bus."

The system can then automatically take precautions — such as shutting the CPU down — before the processor fries. The feature is useful because a 400-MHz Xeon processor and its terminations can dissipate up to 36 W. (Each additional device in a multiprocessor configuration adds another 30 W; the 6 W eaten up by the terminations remains constant.)