EAST FISHKILL, N.Y. — IBM Corp. will use silicon-on-insulator (SOI) technology to manufacture a range of logic ICs, starting with a PowerPC 750 microprocessor in the first half of 1999. By signaling that it is ready to apply SOI technology to volume manufacturing, IBM has set the stage for yet another epic shift in the semiconductor industry, less than eight months after saying it had reached a similar confidence level with copper interconnects.

IBM will combine copper interconnects with SOI transistors in a range of MPUs next year, and expects performance gains of 20 to 30 percent from the shift to SOI. By applying copper, SOI and low-k interlevel-metal dielectrics to the gigahertz processor design unveiled last February at the International Solid State Circuits Conference, IBM expects to be able to push commercial processor speeds to the gigahertz range in two to three years—faster than competitors such as Intel Corp.

And because SOI shines particularly brightly at low-voltage operation, the technology will make it possible to overcome the heat and power-dissipation problems in high-performance ICs, and offer the mobile market a means of delivering reasonable performance at single-volt supply voltages.

In that regard, Motorola Inc. indicated last week that it is not far away from applying SOI as well—initially to high-speed logic, starting with a PowerPC. Motorola also is preparing an SOI BiCMOS process aimed at RF/IF circuits used in cellular phone applications.

Bijan Davari, director of advanced logic development at IBM, said the company has developed an SOI "recipe" that resolves three major challenges: how to implant and anneal an oxide insulation layer in the bulk silicon at minimal defect rates; how to create partially depleted CMOS devices that can handle the "floating-body" effect common to SOI transistors; and how to prepare relatively accurate models and circuit libraries. The models, in turn, have made it easier to convince circuit designers and product managers to take a risk on SOI-based designs.

Davari said IBM believes the use of SOI wafers adds about 10 percent to the overall process cost, compared with bulk silicon wafers, while improving performance by 20 to 30 percent. Those gains stem from a sharp reduction in parasitic-junction capacitance.

One source said as many as 400 IBM circuit designers, working at four different divisions, have been trained in SOI and are working to apply the technology to a range of circuit designs. Davari said the SOI process already is being installed at IBM's Burlington, Vt., manufacturing complex and will be used fairly quickly to build desktop-PC processors operating in the 1.8-to-2-V range internally.

Ghavam Shahidi, SOI program manager at IBM, said many skeptics within the company became believers on Feb. 1, 1997, when a PowerPC 604e processor made on SOI-type wafers was able to boot up a computer. By May 1997 the company demonstrated a PowerPC 750 processor. Later, a four-way server built around four SOI-enhanced PowerPC 750s was able to run the AIX operating system (IBM's version of Unix.).

If IBM's SOI gambit is successful, it could make waves on the systems side. The technology could give IBM's RS/6000 workstations and AS/400 servers—as well as Apple Computer Inc.'s Macintosh line—a significant boost in the market against more mainstream systems using Intel's Pentium and Merced processors.

Keith Diefendorff, who was the chief PowerPC architect at both Motorola and, later, Apple before joining Micro Design Resources, said IBM's announcement is "a really big deal" that puts pressure on Intel.

"You can argue that IBM has gotten a couple of steps ahead," he said. "Copper is a really big deal, and IBM got there well before Intel. They have repeated that with SOI, and the combination of both copper and SOI results in performance gains equal to almost a whole process generation." At 0.18-micron design rules, IBM can apply copper interconnects and SOI-type transistors and get "a pretty big advantage," said Diefendorff.

IBM need not push to the more expensive lithographic tools to achieve a performance boost normally gained by shrinking line widths.

Diefendorff said combining SOI with copper will let chip makers reduce the capacitance on both the wires and transistors, and enable higher-clock-rate processors to operate without burning up. But he said that to get to get to gigahertz speeds, designers must adapt state-of-the-art processor designs to SOI, starting from the ground up.

Diefendorff and others noted that Intel researchers—in their public pronouncements at chip conferences—have been conservative about using SOI.

The long route to commercial use of SOI still faces significant cost hurdles.

IBM started SOI research in earnest in the mid-1980s, when researchers concluded that it would be difficult to scale bulk silicon-based circuits down to low voltages. The effort picked up momentum in 1990, when Shahidi and others demonstrated that a partially depleted CMOS (rather than fully depleted) could overcome the short-channel effect common to fully depleted devices in SOI wafers.

Davari said that currently, IBM implants a thin, 3,500-Angstrom layer of oxide beneath a silicon layer of 1,800 Angstrom on a non-epitaxial wafer. IBM developed a proprietary furnace annealing process step, and the result is wafers with defect rates comparable to bulk silicon at "reasonable" throughput in the wafer-creation stage. Shahidi said the slow process of implanting the oxygen—now done internally at IBM at a rate of about 20 wafers per day per implanter—results in an SOI wafer cost of about $400 to $500, compared with about $60 for a bulk silicon 8-inch wafer. The IBM manager said that cost multiple can be reduced to two to four times with higher-throughput equipment.

Both IBM and Motorola have worked with Ibis Technologies Corp., a Danvers, Mass., company that has developed implantation machines which allow oxygen to be diffused into the silicon with no appreciable increase in defects in the crystal lattice. Ibis sold two implanters to IBM earlier this year for $8 million, and a third unit to wafer manufacturer Mitsubishi Materials Corp. It has also licensed its technology to Mitsubishi Materials in Japan.

Al Alioto, vice president of sales at Ibis, said that at lower voltages the thickness of the oxide layer can be reduced. That would shorten the time needed to implant a single wafer, from five hours for a 3,500-Angstrom layer needed at 1.8-V operation, to 1,000 Angstrom or less, with a proportional reduction in the implant time. That would serve to improve throughput and reduce costs for volume SOI production.

"At 1.5 V you don't need such a thick layer, and then for high-performance CMOS the SOI approach really starts to make sense," Alioto said.

IBM may soon have company in SOI manufacturing. Jim Prendergast, director of Motorola's wireless IC research and development laboratory, said Motorola is "certainly well beyond the pure R&D stage with thin-film SOI. We are looking at products where thin-film SOI has clear advantages."

Motorola has fabricated a test vehicle, believed to be a PowerPC processor, at its Advanced Technology Line in Austin, Texas, which Prendergast said "can be developed for production in 1999."

Motorola also has undertaken a BiCMOS process development in SOI for RF/IF applications. Getting sufficient gain in SOI has been difficult, Prendergast said, and dealing with electrostatic discharge also has been a challenge. He said applying SOI at the 0.15-micron technology generation is on Motorola's technology road map. "Motorola is in quite a strong position in thin-film SOI."

In Japan, Mitsubishi Electric has begun offering samples of a 500,000-gate array in SOI technology. Honeywell's Plymouth, Minn., operation uses SOI technology for space applications and other radiation-hardened circuits, and is extending that work to SOI-based sensors. Peregrine Semiconductor (San Diego) has pioneered silicon-on-sapphire technology for satellite and cellular phone applications.

Fred Zieber, principal analyst at Pathfinder Research, said SOI presents manufacturers with a number of challenges, and it may take two years for some large companies to catch up to leaders such as IBM. "To be able to build something like the PowerPC750, with millions of transistors, is very impressive," Zieber said. "SOI takes a lot of elbow grease, and it takes a company like IBM to pull something like this off." Along with up to 30 percent performance gains, SOI could improve power consumption "30 to 50 percent," Zieber said.

IBM could apply its silicon germanium technology to the analog portion of the cellular phone, use SOI-based logic for the digital portion, and achieve extremely low power consumption.

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