TOKYO — Sharp Corp. confirmed this week that it is pushing SOI into communications ICs and that it will begin a foundry business for SOI devices. Meanwhile, executives at Motorola Inc. told EE Times that the company is preparing a module for its CMOS process that would enable the use of SOI in a design. And design-automation experts also weighed in, asserting that while SOI won't pose many tools challenges, the technology could throw over traditional CMOS-based design methodologies.

Interest in silicon-on-insulator technology surged on the heels of IBM's announcement that it is deploying SOI technology in a version of the PowerPC. IBM officially announced it was using SOI on the PowerPC 750 microprocessor, expected in the first half of next year. This 15-year-old technology, which has long searched for profitable applications, is a way to bring lower power and high performance to high-speed designs.

Officials at Sharp, based here, are promoting a phase-locked loop (PLL) device fabricated on SOI substrates.

"We have established a production system ready for orders, though it is not yet ready for volume production," said Hiroaki Shimizu, division general manager who is head of Sharp's VLSI Development Laboratories.

The prototype PLL operates at 1.2 GHz at a 1.5-V supply voltage. Power consumption is about 3 mW, roughly one-ninth of that of corresponding BiCMOS PLL fabricated on conventional bulk wafers.

Sharp anticipates devices that run at less than 1 V. "We are sure 0.5 V is possible," said Shimizu. "Our final target is mobile equipment that runs with a solar battery."

Shimizu said that according to Sharp's road map, "we are planning to offer all the devices for mobile communicators" — from the front end (RF devices) to baseband processors (DSP and CPU) — "implemented on SOI." The plan is to field a two-chip solution by 2000, he said.

The company also has completed a core CPU implemented on SOI, said Alberto O. Adan, chief technical specialist leading Sharp's SOI project at the labs.

The 50-MHz prototype, which is based on the ARM architecture, consumed 15 mW at 1.5 V, in a 0.35-micron process. According to Adan, the same design in bulk CMOS would consume 60 mW at 3 V.

Sharp uses SOI wafers supplied by wafer manufacturers. "We have been testing various type of wafers," said Shimizu. "Thus far, we believe that the Simox SOI wafer has the highest potential." Simox stands for "separation by implantation of oxygen." Sharp's SOI devices are fabricated on Simox wafers with a 1,000-Angstrom (50-nm) top silicon layer.

"SOI wafers cost about 10 times more than bulks at present," Shimizu said. "Unless the price drops to a range of twice to three times bulk prices, it is difficult to say if the SOI business will pay off." Sharp engineers are hustling to overcome the cost delta by working to increase yields, simplify the process and use smaller geometries.

Sharp intends to grow its SOI business aggressively. As a part of its measures to increase efficiency, the company has decided to begin a foundry business for SOI devices.

Motorola is developing a module on its standard CMOS process that would allow engineers to put down an insulating layer on top of portions of a standard silicon wafer. This layer could then be used as a substrate for SOI circuits. Or it could be used for more mundane purposes, such as providing an insulating substrate for high-Q inductors needed in RF designs.

The purpose of the Motorola development is to get the benefits of SOI technology without having to have an entire separate SOI process, with its own complete set of IP, libraries, tools and so forth. By putting the insulating layer on top of the silicon, Motorola could build a standard CMOS die, one portion of which happened to contain an SOI circuit. The process would only differ from standard CMOS in the added steps necessary to produce the oxide and SOI devices. For instance, an SOI RF front end might be produced in one corner of a CMOS baseband chip for highly compact cell phones.

The development started as research into a novel way of assembling ICs into three-dimensional arrangements, and spun off the SOI-on-Silicon capability. It is in line with the company's over-all goal of reducing the number of specialized processes used across its product lines. Conceptually, the SOI-on-silicon technique could be nearly as flexible as SiGe technology, which permits the designer to choose the performance of individual transistors in a BiCMOS circuit

On the EDA side, vendors said that tools won't be a problem but that methodology might be.

"SOI accelerates what is already happening with deep submicron," said Lou Scheffer, a Fellow with Cadence Design Systems Inc. "A bigger and bigger proportion of your capacitance is coupling to nets instead of coupling to ground, because IBM's SOI just got rid of one of the big grounds by getting rid of the substrate. That puts a lot of pressure on your crosstalk and signal-integrity analysis tools, because they are dealing with a much higher fraction of coupling between the signals as opposed to coupling between the ground. You have to look at the tools to make sure the tools do the right thing when there is no substrate present."

Library vendors also will be affected.

"The intellectual-property people have sort of converged on a consensus CMOS process that is supported by all the Taiwan [foundry] vendors," Scheffer said. "It will be very interesting to see if people who build high-performance pieces, such as microprocessors, actually custom-design to the [SOI] process, which would not be a trivial shift, or stick with the CMOS rules because everyone can build with them."

"That extra oxide layer in SOI is going to translate into how things function," said Ron Sailors, assistant to the general manager at the Epic group of Synopsys Inc. "That means the voltage is dynamically dependent on what is happening, so the capacitance is dynamically dependent [too]. One approach is to add a fifth terminal to the transistor model to handle that floating voltage or capacitance."

Sailors said Synopsys doesn't expect the tool adjustments will be hard to implement.

"If you are a library vendor, for example, you have to make sure all your libraries have been enhanced to handle that extra terminal; if you're a simulator company, you want to make sure your simulator accounts for activity along that fifth terminal; and if you're a process characterization company, you want to make sure that you are accounting for the appropriate capacitance curves," he said. "Anyone who is going to be involved with an IBM or Motorola is going to have to make the appropriate adjustments."