SAN JOSE, Calif. — Startup Stellar Semiconductor Inc. has detailed a 3-D graphics engine that will be capable of a sustained rendering performance of 200 million pixels per second. The single-chip VelaTX rendering engine, which will be described at the Hot Chips Conference in Palo Alto, Calif., incorporates an embedded Multibank DRAM core from MoSys Inc. (Sunnyvale, Calif.). Targeting high-end PC gaming apps, it packs 2.5 Mbytes of embedded DRAM solely to store 3-D textures.

Stellar will pursue both fab and fabless business models. Though the company sees synthesizable 3-D core licensing as a profitable part of its business, it has come up with a family of actual 3-D graphics chips "to generate interest in our intellectual-property core," said Sandeep Gupta, chief executive officer of Stellar Semiconductor (San Jose, Calif.).

The VelaTX is one of the first among a new generation of 3-D chips slated to come to market this year. Embedded DRAM is expected to be pervasive in these new graphics engines, along with proprietary 3-D rendering architectures emphasizing algorithms that select which pixels to render, rather than traditional frame-based pixel rendering. The goal is to raise overall 3-D rendering performance while reducing required memory storage and bandwidth.

Companies like Stellar believe that the traditional frame-buffer approach will soon be unable to support end users' insatiable appetite for faster frame rates and snazzier graphics, said Gupta.

Pivotal to the startup's design is an efficient 3-D pipeline architecture that eliminates the need for a Z buffer. Combining that with MoSys' low-latency Multibank DRAM architecture "has enabled us to develop a higher-performance 3-D graphics chip without increasing the memory size, thus saving the cost," said Gupta.

The chip will be built using Taiwan Semiconductor Manufacturing Co.'s 0.35-micron, memory-based embedded DRAM, Gupta said. Samples will be available in the fourth quarter, with volume production scheduled for early 1999. The price is $35 in lots of 10,000.

Unlike many high-powered graphics chips, the VelaTX does not integrate 2-D graphics capability, but it does come with an AGP-to-PCI bridge. Thanks to a 66-MHz PCI bus, one or two PCI devices can reside behind the VelaTX and communicate with the rest of the system through the advanced graphics port.

Stellar's proprietary architecture, called PixelSquirt, renders one pixel at a time in scan-line order, similar to the way a CRT refreshes its screen. Also used is a patent-pending algorithm that determines which polygons will be visible in a scene and which will not, so that the chip can remove hidden surfaces before any pixels are rendered. The scheme thus eliminates the need for the extra memory usually dedicated to the task of Z buffering, and incumbent rendering of unseen pixels. Stellar has filed four patents on technologies used in PixelSquirt.

Companies such as NeoMagic Corp. already supply the notebook-PC market with graphics controllers that contain embedded DRAM. Micron Technology Inc. (Boise, Idaho), meanwhile, has its sights set on the higher-volume desktop 3-D-graphics market, using its embedded DRAM technology, through the pending acquisition of Rendition Inc. (Mountain View, Calif.).

Despite such growing momentum, many graphics-chip vendors are finding that a 0.35-micron process with embedded DRAM often comes at the expense of logic performance. Few have been able to provide much more than 2 Mbytes of on-chip DRAM cost-effectively.

But Stellar's VelaTX 3 has 2.5 Mbytes of embedded DRAM, with a very wide, 512-bit bus. It's capable of delivering bandwidth of up to 6 Gbytes/second, thanks largely to the elimination of the Z buffer and associated on-chip memory. Also, the low-latency architecture of MoSys' embedded Multibank DRAM inherently makes it easy to achieve a high sustained memory bandwidth.

"Traditional DRAMs have a long precharge and Row and Column access latencies," explained Andre Hassan, director of marketing at MoSys. "By cascading more memory in parallel for embedded DRAM applications, traditional DRAMs could only require more pins, more power consumption and make the DRAM core much slower and less efficient."

Because the latency of MoSys' Multibank architecture is much lower than the statistical row-hit rate, the sustained memory bandwidth will be at peak bus bandwidth, Hassan said. "In fact, widening the bus is not a penalty in our embedded-DRAM architecture. It actually makes sense to go to a wider bus." MoSys' Multibank DRAM core has a 512-bit bus, yielding 8 Gbytes/s at 125 MHz. "Nobody has achieved that level of high available bandwidth," said Hassan.

The MoSys embedded DRAM core used in Stellar's chip offers 6 Gbytes/s at 100 MHz. In closely working with Stellar, Hassan said, "We've ensured that the bandwidth will never become a bottleneck for Stellar's 3-D graphics architecture."

Until now, the MoSys embedded Multibank DRAM was not available as a standard core. Hassan said the company is working with multiple partners that want to embed the core for many applications beyond graphics.

The high-quality rendering performance realized in the VelaTX includes single-pass multitexture-per-polygon, bump mapping and full-screen sort-independent subpixel anti-aliasing. The chip boasts 32-bit full-color resolution for all raster ops, 24-bit floating-point hidden-surface removal and single-pass trilinear texture filtering. It also supports advanced DirectX D3D features in hardware.