TAIPEI, Taiwan — Intel Corp. is ready to detail a path for Direct Rambus memories to find their way into workstations and servers. But server makers here and in the United States are showing some reluctance in just how fast they want to go down that road, especially for high-end systems that might need larger memory sizes and more elaborate error-correction code than Rambus may cost-effectively deliver.

Though Compaq Computer Corp. plans to use Direct Rambus DRAMs in its Alpha-based servers, the Houston company's technology road map is looking for Rambus to deliver a next-generation RDRAM with higher bandwidth, to become available when Merced-class servers hit the market in several years. IBM Corp. hopes to design its own core logic, which will likely support SDRAMs for use with Merced.

For its part, Intel said it expects that desktops — not higher-end workstations and servers — will drive the transition to Direct Rambus, starting with its Camino chip set, set to sample soon. Most Merced-class designs probably will use commodity SDRAM memories, said Pete MacWilliams, a fellow at Intel's Architecture Labs. He expressed confidence the Rambus/SDRAM translation ASICs Intel is designing for next year's servers will be available from a variety of manufacturers, though he was not willing to name names.

That ASIC would allow companies to use SDRAMs on a Rambus in-line memory module, a guard against tight availability, relatively high prices or relative lack of scalability of the RDRAMs in the early going.

"In general, our view is people will use SDRAM in servers and workstations for several years," said MacWilliams. "A lot of servers still use EDO [extended-data-out] memory today. New memory technologies are most needed in the desktop, where there is a small total memory and need for high bandwidth."

Still, he said, "There's no fundamental reason Rambus memories can't be used in high-end servers, it's more a matter of when."

Subodh Toprani, the Rambus vice president in charge of non-PC applications, said the issue of Direct Rambus availability is "rapidly fading away." Toshiba Corp. has announced it will be in volume production of 64-Mbit Direct RDRAMs by the end of this year. LG Semicon and Samsung in South Korea, and NEC in Japan, are on a similar schedule. Toprani argued that by the first quarter of 1999, "four heavyweights in the DRAM business will be making RDRAMs in volumes."

The current Rambus specification permits either 16- or 18-bit configurations to support error correction. Toprani said when Rambus shopped a specification that supported high reliability, the server manufacturers said they preferred to use their own solutions to the reliability question. Server makers must ensure system availability when one device fails completely.

Intel expects to visit OEMs here in September to begin detailing plans for how to bring Direct Rambus to what it calls "mid-range" servers, using the Carmel chip set that's slated to appear in production samples in July 1999. The Carmel memory controller will support two Direct Rambus channels, which can connect to a total of eight Rambus or SDRAM memory repeater hubs. That could open the door to systems with as much as 4 Gbytes of main memory, using 128-Mbit Direct RDRAM parts or 8 Gbytes of RAM when 256-Mbit parts become available.

"Carmel can support only 2 Gbytes of system memory without the use of repeaters," said the head of R&D at one of Taiwan's leading mainboard manufacturers. "With the use of repeaters, [Carmel can support] four repeater banks."

Sources familiar with the Rambus technology agree. "ASICs are needed to buffer loading in order to achieve 4- or 8-Gbyte system memory sizes," said another source.

Toprani said that when 256-Mbit devices become available, each channel can support 1 Gbyte of memory. He said all memories, whether SDRAMs or any others, will require some buffer scheme at very high memory densities.

The use of either RDRAM or SDRAM is made possible by an ASIC or repeater hub that acts as a translator between Rambus channels on Carmel's memory controller and PC-100 SDRAMs on a modified Rambus in-line memory module (RIMM). Each repeater hub can connect to as many as two SDRAM or Direct Rambus memories, and one or two RIMMS with two repeater hubs can be linked to a single Rambus channel from the memory controller.

"There is certainly concern about having multiple quality suppliers" for RDRAMs and translation ASICs, said Tom Bradicich, program director for PC server architecture and technology at IBM.

"The question is does the buffer [ASIC] exist," said Dean Klein, chief technology officer at Micron Electronics (Boise, Idaho). "It's an idea on paper right now."

Without the potentially cost-adding and difficult-to-source ASICs, Carmel-based systems could be limited to 2 Gbytes of RAM, said Klein. But OEMs want to ship the systems with 4 to 8 Gbytes of main memory next year.

"The solution I think most people would like [for next year's PC servers] is good old SDRAM and plenty of it, backed up by these conversion buffers," added Klein. "We would prefer to use SLDRAM in servers and workstations and think there's a consensus of some others with the same belief among non-X86 vendors." However, Klein said he was not aware of anyone who had a license to Intel's key P6 bus technology to design core logic that would use SLDRAMs with the so-called Tanner CPU, due out next year.

The Carmel core logic is aimed at Tanner, a follow-on to the Pentium II line that will initially top 500 MHz and sport 100- and ultimately 133-MHz external buses.

Which system bus speed to use in a server will be a major consideration next year. "Four CPUs at 100-MHz bus speeds is optimum theoretically," said Jeff Shu of First International Computer Co. (FIC). "Currently though, few programs have the multitasking threading necessary to maximize the use of more than two CPUs. Personally, I'd rather buy a two-CPU server running at a system speed of 133 MHz. I save the money of the extra two CPUs."

Whether SDRAM can run effectively at 133 MHz is another question. Several engineers in both mainboard and core-logic companies here doubt that SDRAM can handle the multitude of timing latencies among the different signals inherent to SDRAMs at 133 MHz.

When it comes to Merced servers, both Bradicich of IBM and Karl Walker, vice president of technology development for Compaq's Enterprise Computing Group, said Direct Rambus memories as they exist today probably won't meet their needs. Compaq is exploring its options with Rambus and other memory makers, Walker said.

For its part, IBM is looking to tap commodity memories — likely SDRAMs — and leveraging error-correction code (ECC) technologies from its mainframe and RISC-based server lines. "Specifically in the medium- to high-end servers where Merced plays, Rambus does not lend itself to standards or reliability and availability," Bradicich said.

IBM plans to tap into several ECC techniques used on its non-Intel systems, such as chip kill, which lets systems run despite a frozen 4-bit memory cell; bit steering, which adds on a redundant bit in a failure; "and a few other proprietary things we are working on now," said Bradicich. "You can do these things with Direct Rambus, but at a price."

Indeed, Direct Rambus DRAMs already offer some ECC features and apparently more are to come. "The pursuit of extending Rambus is going on, but we are not going down that road" for high-end servers, said Bradicich.