SAN JOSE, Calif. — As IBM, Sharp, Motorola and others prepare to use silicon-on-insulator (SOI) semiconductor technology, EDA vendors have looked at the implications for design tools and concluded that SOI doesn't pose huge tool challenges, but will require new models and possibly new methodologies.

Representatives of both Cadence Design Systems Inc. and Synopsys Inc. said the biggest challenge may be for library vendors, simply because it takes time to develop libraries. Avant! claims to have already developed SOI libraries with an unidentified company, and to have put the libraries through Avant!'s place-and-route flow.

Lou Scheffer, Cadence fellow, said the company's R&D wing had not been looking explicitly at SOI but expects it will take a serious look at it now. "SOI puts a lot of pressure on your crosstalk and signal-integrity analysis tools, because they are dealing with a much higher fraction of coupling between the signals as opposed to coupling between the ground," he said. "You have to look at the tools to make sure the tools do the right thing when there is no substrate present."

Scheffer expects the company to make changes to its Hyperextract interconnect extraction tool and Vampire extraction tools to deal with SOI.

SOI also poses some methodology challenges, he said. "What people have been doing is avoiding the cross-coupling problem," said Scheffer. "For example, they would place very strict slew limits on their methodologies and that makes the placement tools keep the nets short. But when you have SOI, some of those slew limits won't work so well. You will have to do a direct analysis of cross-coupling voltages."

Ron Sailors, assistant to the general manager at the Epic Technology Group of Synopsys, said that for some time Synopsys has been looking at SOI and the tool and methodology challenges it presents.

"The tools have to change a little bit to accommodate SOI — it all stems around the modeling," said Sailors. "That extra oxide layer in SOI means that the voltage is dynamically dependent on what is happening, so that means the capacitance is dynamically dependent. One approach is you add a fifth terminal to the transistor model to handle that floating voltage or capacitance."

Sailors said that the company doesn't expect the tool adjustments will be hard to implement.

"If you are a library vendor, for example, you have to make sure all your libraries have been enhanced to handle that extra terminal; if you're a simulator company, you want to make sure your simulator accounts for activity along that fifth terminal; and if you're a process-characterization company, you want to make sure that you are accounting for the appropriate capacitance curves. Anyone who is going to be involved with an IBM or Motorola is going to have to make the appropriate adjustments," he said.

Kevin Walsh, head of product management for analysis products at Avant!, believes that SOI won't really require a tool shift, but may affect models. Walsh said Avant! has been active in working with companies developing SOI. It worked with Sharp on an SOI model, he said, in addition to collaborating with an unnamed company on creating an SOI library.

Walsh said the recent SOI announcements "may be the beginning of some fundamental change where low power and gigahertz collide in the same devices."