SANTA CLARA, Calif. — Intel Corp. and a group of top PC makers are pushing the future of the PCI bus in different directions. A debate over PCI is now brewing in the arena of high-end PC servers, but promises to spill over into communications and embedded systems designs.

Intel is planning a PCI upgrade that will differ from PCI-X, an incremental upgrade that specifies an increase in PCI speeds from 66 to 133 MHz. Unlike PCI-X, which was drafted by Compaq Computer Corp., Hewlett-Packard Co. and other computer makers, Intel's unannounced upgrade to PCI does not involved a move to 133-MHz speeds. Intel received a copy of the PCI-X specification, also called PCI-133, on Aug. 31, an Intel spokesman said.

Separately, Intel is focusing on the rollout of a concept for a gigabit-class serial bus that would be a radically different, long-term follow-on to PCI. Intel will outline the approach, tentatively dubbed next-generation I/O (NGIO), at its Intel Developer Forum (IDF) next week. NGIO aims to bring mainframe-class links to PCs, internetworking gear and networked peripherals.

PC makers are concerned about Intel's NGIO plan, and with the cost and other issues related to introducing a new bus that is incompatible with PCI, according to one PC engineer from a company that backs PCI-X, who asked not to be named. "We are trying to avoid bringing any high-end incompatible buses into our PC servers," said the engineer, noting that many Unix-based servers use proprietary high-end buses. "We are having problems with the bandwidth of PCI, but we want to get to something that is a straight shot from PCI."

Intel would have to absorb some costs to design core logic for NGIO, the engineer said, but PC and peripheral makers would bear even greater costs in moving to the new architecture. "The costs grow exponentially as you move out into the industry," he said. "Anything that is incompatible is a big problem for the industry to pick up."

Intel is not necessarily against the PCI-X proposal, but it had been planning its own upgrade for PCI that didn't rely on doubling the speed of 64-bit, 66-MHz chips that are now starting to ship. Intel had planned a proposal to modify the PCI protocols in a way that would let PCI controllers and PCI cards communicate with one another in a way that would reduce bus contention and make communications more efficient. The Intel proposal would not require moving to 133-MHz speed, and could be made backward compatible with existing PCI standards, according to Mitch Shults, director of server-platform marketing at Intel (Beaverton, Ore.).

It's not clear whether Intel will go ahead with its interim PCI plans or try to work with the PCI-X spec. The company received what Shults called "a thick document" describing the PCI-X spec only last week. "We haven't completed our assessment of it yet," he said. "Conceptually there's value in continuing to advance PCI, but we need to look at how they are doing it. We've known about [PCI-X] for a long time, but we didn't know they were that far along."

Whatever next step PCI takes, Intel believes the PC must ultimately get off from the parallel, shared, memory-mapped bus to move to what Shults describes as a fast serial bus unchained from host interrupts and better characterized as a mainframe-like channel or switching fabric linking a processor complex to internal and external systems peripherals — which is the goal of NGIO.

"There's a general recognition that we have to move I/O to a higher plain. We have to get to a more mainframe-like channel-based architecture," Shults said.

At IDF, Intel will talk publicly for the first time about NGIO, which has yet to receive a final name. The company will demonstrate the concept using message-passing software derived from the Intelligent I/O and Virtual Interface Architecture specifications. Intel engineers will also describe the concept of the I/O technique for PCs that will not use interrupts. The company will not detail specific hardware implementations or discuss chip sets or products at the Forum that will use the technique. "Its too early for that," Shults said.

"We want to build an I/O architecture for standards-based servers that lasts for the next 30 years," he added. "The whole point is to manage overhead in connections out from the processor complex to peripherals."

Shults said the new interconnect could be used in Internet servers and routers so that a Web server could use the I/O link to connect its processor complex directly to the backplane of a router, to a disk farm, or to a RAID array without using TCP/IP protocols or other software overheads.

Intel is working with partners to define its NGIO, Shults said, but it wasn't clear given the current controversy over PCI-X if any of those partners would be named at IDF. However, as with PCI, Shults said, the partners would contribute technology on a royalty-free basis. "Broad adoption is more important than royalty streams," he said.

Intel's Gbit-speed serial bus approach is aimed at solving the "long-term limits to parallel buses" that must necessarily limit the number of slots and the distances of the bus as speeds are extended. "The PCI-X proposal may demonstrate a faster parallel bus, but they have not discovered a way around the laws of physics," said Shults.

In the near term, Shults noted Intel is just starting to ship chip sets that use a 64-bit, 66-MHz version of PCI. "There are lots of 64-bit slots with 32-bit cards in them out there. The industry needs to catch up to the existing hardware."

A separate group of VMEbus embedded systems developers is trying to define a "dataflow" architecture that could use concepts similar to Intel's NGIO. The VITA Standards Organization (VSO) has a working group that consists of as many as 25 companies, working mainly in the military and telecom areas, who are defining a distributed computing architecture.

The VSO group has settled on a physical design and connector scheme, but has yet to define the electrical and logical elements of a 2- to 3-Gbit/second serial bus that could drive the design. "If Intel comes out with something that uses 5,000 gates and costs $5, that's what I want to use," said Ray Alderman, chairman of VSO. "I certainly don't want to build something from scratch if there will be a mainstream option."

There are real engineering challenges to building a gigabit class serial bus, said Alderman, who had a hand in such an effort when he served as chief executive of a board company that developed the Autobahn bus. Despite the challenges, Alderman said the future of computer I/O rests on fast serial buses.

"Instead of centralized I/O managed by a CPU, which adds complexity, you go to distributed I/O that uses packets," said Alderman. Such a design could relieve developers from writing operating-system-specific drivers, since the systems would not depend on low-level control of CPU interrupts that could radically changing the software model.