OTTAWA, Ontario — Solidum Systems Corp. has developed a way to perform high-layer network packet processing that is less expensive than using dedicated address-resolution-logic processors or off-chip content addressable memories, the company said.

Solidum is proposing a language — the networking equivalent of a hardware-description language — that reduces packet header information into a simple state graph, thus allowing packet processors to be implemented in cheap programmable state machines.

Solidum faces two barriers to acceptance: it must convince users to adopt the PAX packet-description language (PDL); and it must show that the chip-level implementations it provides are more efficient and economical than embedded RISC processors or massively parallel route engines. Customers need little convincing on the latter point, said Misha Nossik, vice president of Solidum, which was founded by veterans of RAD Communications Inc.

"The problem is still so acute, even if they have not adopted our method, they tell us, 'I wish you had approached me with this idea a year ago,' " Nossik said.

Nossik and Solidum president Feliks Welfeld began working on the concept in the fall of 1996 while developing a wire-speed packet analyzer for RAD Network Devices. A software implementation of a Layer 3 and 4 packet analyzer was attempted, but performance declined precipitously after more than three filters were used, Nossik said.

In 1997 the two designers decided to create a company dedicated to promoting PDL as a way to simplify state machines for complex routing duties. Solidum was financed through bootstrap and private funding, rather than through venture funding.

The design team briefly toyed with the idea of using PDL with massively parallel architectures. But "it made far more sense to represent the state-space to map in a finite, cost-effective way," Nossik said. "We have implemented a packet analyzer in a 1,000-gate hardware block that can assess routing rules up to Layer 4, and represent the rules in less than 2 Mbytes."

Solidum has designed its own network interface card, using an FPGA state machine on a 10/100 Ethernet card. Solidum will take its PDL formats to relevant standards bodies like the Internet Engineering Task Force, but the company is still open minded on the issue of hardware vs. behavioral macros for deliverables to customers.

"Our business model calls for licensing a VHDL macro, but our view is that the spiral of development is going back to standards-based platforms," Nossik said. "We are assuming customers want compilers, a full development kit for the language, and a reference hardware design, as well as chips."

As it stands today, the PAX PDL can support option header fields for both IPv4 and IPv6. The current receive-side ability to handle packet modification will be enhanced with a full transmit and receive ability to modify packets in richer extensions of the PDL. Art Collmeyer, president of compression chip specialist Hi/fn Inc., has joined the Solidum board. Nossik said there could be interesting combinations of the PAX PDL and state machine with the Hi/fn compress and encrypt model, with Solidum adding a "classify" function for packets prior to compressing and encrypting.

Competitors to the scheme could range from packet processor chip specialists like Softcom Microsystems Inc. to associative-processing algorithm experts like NeoCorem. "We don't see people working on packet header abstraction concepts yet," Nossik said. "Many people assume that implementing these functions in a state machine is simply impossible, so they give up before studying the problem."