LAUSANNE, Switzerland — Cadence Design Systems Inc. (San Jose, Calif.) may be on the brink of releasing ground-breaking EDA software that could accelerate system-level design, according to sources at the recent System-Level Design Language workshop.

Cadence is reportedly prepping a product called Virtual Component Codesign (VCC) stemming from its "Felix" initiative. That project, made public last December, promises to let designers confirm key architectural decisions, such as hardware and software partitioning, early in the design cycle.

A prototype for a specification environment that uses the hybrid Esterel-C language has been implemented in a product designed to handle the integration of intellectual property, and is now being worked on by Cadence's legal and marketing departments, sources here said. VCC will make it possible to simulate, optimize and synthesize hardware-software designs described in terms of "communicating finite state machines." A parser to automatically separate Esterel-C into constituent parts has also been completed, along with an Esterel compiler.

All these manipulations happen before hardware-software partitioning, much earlier in the design process than is standard practice today. The simulation capability allows engineers to explore different architectures and estimate key parameters such as performance vs. power consumption. The subsequent synthesis can be to a mix of hardware and software.

During her presentation of a paper on Esterel-C, Ellen Sentovich of Cadence Berkeley Labs said that the Felix product launch was imminent. "VCC is the new name for what was affectionately known as Felix, now that legal and marketing have gotten involved," she said.

Officially, however, Cadence was keeping mum. "There are no immediate plans at this time for a general launch of the Felix initiative's VCC products," a spokeswoman said. "The Felix initiative is going very well, and R&D efforts are now focused on pilot projects with our initial partners." Project participants include ARM Ltd., BMW, Debis Systemhaus, Ericsson, Magnetic Marelli, Motorola Semiconductor, National Semiconductor, STMicroelectronics and Symbionics, which is now part of Cadence.

The spokeswoman emphasized that Felix technology, when commercialized, will support multiple methods of design capture, and said that Esterel-C is "only a small part" of the technology portfolio.

Though Cadence declined to provide any specifics about VCC, Sentovich's paper suggested a context in which it could be used. She described a design flow from a systems-level specification in Esterel-C, a combination of the Esterel language developed by a team under Gerard Berry of the Ecole des Mines de Paris (Sophia Antipolis, France) and the familiar general-purpose programming language C, which is already widely used for system modeling.

The Esterel-C description can then be parsed into two separate file formats, one in Esterel (for reactive statements, concurrency and reactive C loops) and one in C (for non-reactive loops, or data modules implemented in C and called by Esterel modules). From there, Sentovich said, an engineer would use an Esterel compiler, which changes the design representation to a format called Shift (software-hardware intermediate format) to describe the design as communicating finite state machines.

Sentovich said VCC takes the Shift format and provides simulation, optimization and synthesis to a hardware-description language and/or software. Cadence Berkeley Labs worked on the Esterel-C parser, while the Esterel compiler is joint venture between Cadence and Berry's group at Ecole des Mines.

At the moment the Esterel compiler translates as much of the design as possible into Esterel for full synthesis and optimization. Sentovich's paper says that further research will explore schemes in which only a minimal part of Esterel-C is translated into Esterel. This will provide benefits in handling legacy code and software implementation.