ROCHESTER, N.Y. — ASICs are the past and systems-on-a-chip (SOC) are the future, according to Raul Camposano, chief techincal officer of Synopsys Inc., addressing the 11th IEEE International ASIC Conference.

As such, Camposano outlined the technical environment he foresees for SOC designers and discussed the tool requirements that Synopsys anticipates for the new world of circuitry.

Camposano nearly dismissed the much discussed problems of deep-submicron design that have been cited as barriers to SOC success. Basing his view on an unpublished paper by the Berkeley Nexus Group, Camposano said that the three great concerns of deep-submicron work — the dominance of interconnect delay, the escalation of power density and the unmanageability of signal integrity issues — were all going to be non-events.

"For moderate-sized blocks of 50- to 100-k gates, interconnect delay at 0.25 microns is on the average only 25-to-40 percent of the total delay if the nets are properly driven," Camposano said. "This figure will get smaller, not larger, below 0.25 micron, partly due to the introduction of copper and low-k dielectrics. This is not true for global interconnect, of course, but global interconnect is already taken into account in today's methodology."

Camposano similarly dismissed concerns over power density, stating that the Berkeley study showed it decreasing, not increasing, with density. And signal-integrity issues, he said, could be entirely dealt with by modeling them as additional delays. "Basically, if you wait long enough, the signals will settle," he said.

While there was some dissention to his views from the conference's audience of ASIC designers, Camposano cleared the issues away to his satisfaction and pressed on to describe what he believed was the proper tool set for SOC design.

SOC design needs to proceed at three different levels, Camposano said: system, RTL and physical. Each of these levels has its own evolving set of tools today.

At the system level, C++ and Java appear to be emerging as the de facto languages, despite academic work on system modeling languages, Camposano said. Designers are adding classes to these object-friendly languages to deal with hardware issues such as bit-width and concurrency. But this is creating a discontinuity between system-level and RTL tool chains.

"If you work in C++ or Java, you can't expect a totally automated path to implementation," he said. "But we can narrow the gap between system and RTL designers. Today, the methodology is to throw away the system code and rewrite it in an RTL language. In the future, the methodology will be to refine the system design in the C++ or Java until it reaches implementation quality."

Beyond this, Camposano restated the announced Synopsys plan to integrate front-end floor-planning tools with synthesis, rough placement and routing, and rough timing extraction. This integration appears to be the best way of reducing design iterations, he said.

The speaker also described synthesis not as a standalone tool, but as the center of an increasingly rich cluster of tools, including datapath generators, state machine compilers, scan and test tools and power estimation tools.

He further said that there is a growing trend back toward flat — as opposed to hierarchical — synthesis of designs. "The trend is toward flattening the hierarchy. We need to synthesize at least a million, and perhaps 4-to-5 million gates flat. As synthesis gets more closely integrated with placement and routing, synthesis has to work on the same size of blocks as the back-end tools."

Along these lines, Camposano hinted at developments for the immediate future. "Design Compiler 98 was from three to 10 times faster than previous versions," Camposano said. "We now have in beta another version that will increase that speed by another factor of three to five, at some sacrifice in synthesis quality. It's the last 1 percent of area optimization that takes all the time. If you don't need that much optimization, you can go faster."