BEAVERTON, Ore. — ModelSim Elite Edition 5.2 from Model Technology Inc. (MTI) is the first product to receive the "Library Tested and Approved" designation from SI2 Labs, according to the Silicon Integration Initiative (SI2) and Mentor Graphics Corp., parent of MTI.

SI2 Labs, formerly the ASIC Test Lab, was established in October 1995 by SI2's ASIC Council to qualify EDA tools for inclusion in the design flows of ASIC Council members.

Andy Graham, president of SI2, said ModelSim is the first Verilog simulator that conforms to the library regression tests established by the collaborative effots of five participating vendors — IBM, Lucent Technologies, LSI Logic, Motorola and VLSI Technology.

Don Cottrell, vice president of technology at SI2, said the "Library Tested and Approved" designation indicates that the ModelSim simulator properly handles the function and timing of cells of the participating vendors' ASIC libraries and conforms to the formal IEEE Verilog HDL standard, and to the language parameters used by Verilog-XL, the de facto standard Verilog simulator from Cadence Design Systems Inc.

The designation is the first hurdle to complete on the way to achieving full ASIC vendor sign-off, Cottrell said. SI2 Labs only performs library regression tests at present, but may add flow and design tests to its repertoire in the future, he said.

Si2 now has each participating vendor evaluate how a tool interacts with other tools in its design flow, and how the tool under evaluation works — in terms of performance, ease of use, and memory usage — in real-world situations, Cottrell said.

MTI's R&D staff worked with SI2 Labs for four months to make sure ModelSim Elite Edition 5.2 was compliant with the labs' requirements and would obtain the SI2 designation, said Dave Kresta, marketing manager at MTI. The tool conforms to Verilog library standards, and to the IEEE and real-world XL, Kresta said.

MTI is contemplating adding a series of switches to the next version of ModelSim that would allow users to fine tune the tool for conformance to the particular standard of a given ASIC house, Kresta said.

SI2 presently has event-driven and cycle-based Verilog and VHDL simulators from all major EDA vendors and plans to evaluate many of them. Cottrell declined to say which companies' tools are currently being evaluated, but said another tool is expected to receive the official "Library Tested and Approved" designation in the coming months. Cadence's Verilog-XL is not among the tools being formally tested at SI2 Labs, but rather is considered the Verilog simulator benchmark, he said.

Si2 Labs has gone through three rounds of funding since it was established in 1995. The first two rounds came from ASIC Council member companies, and the third round was co-funded by ASIC Council members and EDA companies.