WALTHAM, Mass. -- Lexra Inc. has begun beta deliveries of its first synthesizable CPU core . The LXR-4080 is a 32-bit, MIPS-I compliant integer processor designed from the ground up to be synthesized into a licensee's 0.35- or 0.25-micron ASIC or customer-owned tooling (COT) chip design.

The new core is rated at 100 MHz, which vi ce president and chief technical officer W. Pat Hays called a conservative figure based on back-annotated timing. The core design executes the MIPS-I instruction set, without floating-point, multiply, divide or unaligned loads and stores. It uses a five-stage pipeline and requires only 1.8 mm2 in die area for the core, fewer buses, interfaces, caches and so forth.

Lexra recognized that customers would want to exercise a lot of flexibility in using a MIPS core. On the other hand, the company had no interest in being drawn into the custom design business by requests to change the core itself. So the company took a modules-and-interfaces approach to making the 4080 flexible.

A Custom Engine Interface (CEI) connects directly into the 4080 pipeline, giving an external execution unit access to the pipe's A and B operands, Result bus and timing. This interface can be used to implement simple, single-cycle or multicycle instruction-set extensions. Lexra, for example, provides multiply-and-divide hardware for the CEI. Customers could use the interface to wire in a multiply-accumulate instruction, a parity check or other simple custom hardware.

The design also provides a local instruction bus and data bus from the core, making it, strictly speaking, a Harvard machine. Three types of interfaces connect customer-designed circuits to these buses.

First, there may be several instances of local memory interfaces, which may be used to attach instruction and data caches--mandatory in the current version of the design--as well as local SRAM and local ROM. The local memory, like the cache, operates at CPU speeds, providing a facility similar to lockable cache areas, but without the complexity or loss of performance.

A Lexra Bus Interface (LBI) provides a connection between the 4080's local instruction and data buses and the outside world, which in this case would be the rest of the customer's chip.

Finally, a coprocessor interface provides a means for customers to attach coprocessing hardware too complex for the CEI. This is where a vector processor, motion-compensation engine or similar goody could be bolted on.

For ASIC customers, Lexra will provide a synthesizable form of the core for use with the ASIC vendor's libraries. For COT customers, Lexra will adapt the core to the customer's own libraries. In addition, the COT customer has the option of getting significant portions of the core--mainly the register files and pipeline staging logic--in a hard macro form, reducing the size of the core and improving the speed.

The core has been placed and routed in its various forms, but Lexra is still waiting for first silicon on a prototype. The chip will be available for development once it is back and tested.

In the future, Lexra will be offering additional parts of the core as hard macros. The company also plans to include a debug module at about midyear and to add cache-coherency logic for designers who are using multiple instances of the core on one memory system.

Fees range from $210,000 for a one -time design license to $550,000 for an unlimited license. This compares with approximately $1 million for a MIPS license or $500,000 for an ARM-7 design-use fee, according to Lexra. The synthesizable design is available now for beta customers.

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