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eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.


  eeDesign Exclusives
Practical Power Network Synthesis For Power-Gating Designs
The article describes a method for properly sizing sleep transistors in power network synthesis. It introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.More »

  Headlines for Friday Sep 5, 2008
Business
  • Dell outsourcing plan may be tough to execute
  • SemIndia forms JV with Singapore's Jurong Technologies
  • Chrome could spark battle over Web tools
  • Microfabrica raises $22.5 million in Series B
  • TSMC faces weak Q4, big utilization dip, says analyst
    Technology
  • Virtual mixer harnesses DSP
  • Technology Week in Review: No more Bell Nobels, robotic surgery, anti-cloaking
  • Peratech touts polymer based RFID security material
  • Video enhancement algorithms on embedded systems
    Products
  • Learning from iPod, Zune and iPhone failure modes
  • Tool targets metamaterial based wireless designs


      Headlines for Thursday Sep 4, 2008
    Business
  • Has Imagination followed ARM's lead with Apple license?
  • Innovative Silicon grabs former Spansion CTO
    Technology
  • Fairchild to address energy efficiency at Embedded Power Conference
  • Comment: When atoms count
    Products
  • UWB to ship in wireless HD-video role
  • Startup introduces 'unclonable' chip technology


      Headlines for Wednesday Sep 3, 2008
    Business
  • Gartner lowers 2008 IC forecast
  • Chipidea founder Jose Franca resigns
    Technology
  • Researchers grow nano-scale wire nets
  • Digital signal processor chips embrace multicore ... again
  • IBM, EMC storage gurus debate future of flash
  • Flow memory manages multimedia embedded systems
    Products
  • Garmin Nüvi 205: Entry-level GPS in the great wide open
  • Digital signal processor chips embrace multicore ... again
  • Arris expands R&D at Irish operation
  • Percello femtocell baseband to use Ceva DSP core
  • IPextreme rolls cJTAG IP core
  • Quad SerDes integrates clock jitter cleaner
  • Chrome reflects Google's youthful ambitions


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      Design Resources
    Designing for a dual Galileo-based GPS system
    Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
    More »
     

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