United Business Media EE Times


Search

HOMEMARKET INTELLIGENCE UNITFORUMSDESIGNNEW PRODUCTSCAREERSBLOGSCONTACTEVENTSSIGN UP!RSSMost Popular contentTrusted Sources

 


ESL may rescue EDA, analysts say
Print this article Email this article Reprints RSS Digital Edition

Page 1 of 2
EE Times


ANAHEIM, Calif. — Electronic system level (ESL) design tools may return the EDA industry to double-digit growth, according to two Gartner Dataquest analysts at the Design Automation Conference (DAC) here. But significant challenges remain, both said.

Gary Smith, chief EDA analyst at Gartner Dataquest, and Daya Nadamuni, senior analyst, both presented their views of the EDA industry at the annual Sunday evening Dataquest forecast meeting. Smith opened by saying that the two were using a "good cop, bad cop" strategy and that he was the "bad cop" giving the EDA industry a "reality check."

Smith said that the EDA business model has always been an outsourcing model, but people forgot that in the late 1990's. Because it's an outsourcing model, Smith said, in-house tool development both precedes and defines commercial tool development and pricing. "Customers really don't care how much value you [EDA vendors] bring to the design process," he said.

Further, Smith said, EDA tools today are undervalued because of an "incredibly stupid price war" among EDA vendors.

Smith also said that mainstream EDA users, who bought half of EDA tools in 2001, are getting out of IC physical design, and leaving that to ASIC vendors or consultants. These designers, said Smith, would really like to work at the electronic system level and sign off at the register-transfer level.

But Smith foresees a pickup in the EDA market after five years of nearly flat growth. He predicted EDA worldwide revenues will rise from $3.97 billion in 2005 to $7.46 billion in 2009.


Figure 1 — Gartner Dataquest projections of EDA industry revenue

Even so, Smith said, the use of in-house tools is growing. He said that 27 percent of designers use in-house tools today, up from 20 percent in 2001. One reason, he said, is the lack of available tools for the 65 and 45 nm process nodes.

"Tools should be on the market 18 to 36 months before the first production on the new node," he said. "We're late. We should have the 65 and 45 nm tools now, and we're just starting to see them."



Page 2: ESL to the rescue

Page 1 2




  Free Subscription to EE Times
First Name Last Name
Company Name Title
Email address
  Click here for your Free Subscription to EETimes Europe
 
CAREER CENTER
Looking for a new job?
SEARCH JOBS
SPONSOR

RECENT JOB POSTINGS
CAREER NEWS
SRC Expands R&D Centers
The Semiconductor Research Corp has added a new center to its university R&D efforts.

For more great jobs, career related news, features and services, please visit EETimes' Career Center.


All White Papers »   

  Design Resources
Designing for a dual Galileo-based GPS system
Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
More »
 
Education and
Learning


Learn Now:












Home | About | Editorial Calendar | Feedback | Subscriptions | Newsletter | Media Kit | Contact | Reprints|  RSS|   Digital|  Mobile
Network Websites
International
Network Features




All materials on this site Copyright © 2009 TechInsights, a Division of United Business Media LLC All rights reserved.
Privacy Statement | Terms of Service | About