Almost every week comes news of some new design-for-manufacturability (DFM) startup, tool or technique. There's one problem with all this activity. With so many companies going in so many different directions, it's difficult to figure out what DFM actually is.

The goal is clear: designing chips that will actually yield and do what the designers intended. But this problem is so complex that it calls to mind the proverbial three blind men and the elephant. Some seem to think that DFM is all about resolution enhancement techniques, like optical proximity correction. Some identify it with routers that can perform tasks like wire spreading or via doubling. Others look at DFM in terms of yield simulation, analysis or optimization. Still others might speak of the need to model random and systematic manufacturing variability due to process, voltage and temperature.

How inclusive?
Is statistical timing analysis, which can tell whether a chip will yield at a given frequency, a DFM tool? How about leakage-power or signal-integrity analysis? In some ways, almost every IC design tool you can name is somehow associated with DFM.

Even Gary Smith, chief EDA analyst at Gartner Dataquest, is having trouble figuring it out and is threatening to drop DFM as a category. "We're going to wait a year, but if something doesn't come up, I think we'll change our DFM subapplication to DFY [design-for-yield] and drop the term DFM. It's causing too many problems with data gathering," Smith said.

The last thing chip designers need is to have to become manufacturing experts. Designers want their chips to yield, but they'd like existing tools to handle this problem as transparently and automatically as possible. A technology file for a router might do fine.

DFM point tools are everywhere, but where's the flow? Coming up with one will require a broad-ranging effort rooted in standards such as OpenAccess and Oasis-not a crazy quilt of point tools whose only commonality is the DFM label.

Richard Goering (rgoering@cmp.com) is group editorial director for design automation at EE Times.