A picture is emerging of how the semiconductor industry is going to get chips out the door at 45 nanometers and below. There are three aspects: design-for-manufacturing (DFM), restricted design rules (RDRs) and defect-tolerant or "self-healing" chips.

Certainly, the challenges are immense. Designers will be cramming huge capacities into tiny structures, coping with a broad range of process variations and trying to avoid manufacturing defects. Timing, power, signal integrity, leakage current, thermal gradients and reliability problems (like electromigration) will all warrant analysis.

DFM applies to a broad range of technologies, but the overall idea is to design chips that have adequate yields. Today much of the focus is on resolution enhancement technology. Tomorrow the emphasis may shift to parametric yield, or determining whether a chip meets power and performance goals across process variations.

But DFM alone is not enough. Design rules are restrictive, and there will be further restrictions at 45 nm and below. At one extreme are regular, PLA-like architectures in which everything is on a single pitch and single orientation. More likely, perhaps, are restricted gate pitches and orientations, plus minimum-spacing requirements.

The right combination of DFM and RDRs should produce chips that yield, but the job isn't done yet. Electromigration, hot-carrier degradation and thin gate oxides will be more likely to cause failures in the field at 45 nm and below, calling for some level of defect tolerance. That's the rationale behind Semiconductor Research Corp.-funded research into chips that can diagnose and fix their own defects (see Aug. 28, page 1).

Some might say that any one of these three--DFM, RDRs, defect tolerance--will reduce or eliminate the need for the other two. But I don't see it that way. Like the legs of a three-legged stool, all will be needed as the industry moves toward smaller process geometries.

Finding the right combination, and evaluating the trade-offs, will be a challenge for IC design teams of the future.

Richard Goering (rgoering@cmp.com) is managing editor of design automation for EE Times