There has been much talk in recent years about standards that help chip designers integrate silicon intellectual property into chips. But there's no similar effort on behalf of pc board designers, who are struggling to cope with parasitic package inductance and a lack of information from IC and FPGA vendors.

With today's fast edge rates and wide data buses, parasitic package inductance can easily give rise to ground bounce and Vcc bounce on the board. When that happens, you're pretty much looking at a board respin with a different component. The result may be a delayed product, millions in re-engineering costs and, in extreme cases, a failed company.

What many board designers find most upsetting is the lack of package models and packaging-effect information forthcoming from IC and FPGA vendors. Without good 3-D electrical models, data sheets and support, it's hard to predict when a chip won't work on a given board design.

In the chip design world, silicon IP blocks are analogous to the components placed on pc boards. But silicon IP and EDA vendors have come together to address integration problems. The Virtual Socket Interface Alliance (VSIA) has adopted a number of standards over the years, including checklists of recommended deliverables, such as models and data sheets, that are supposed to accompany the silicon IP. More recently, the Spirit consortium announced a standard XML format for IP integration data.

There are far more board designers than chip designers, but there's no effort comparable to the VSIA or Spirit with respect to packaging data. The challenges for the board world are similar to those addressed by the chip efforts: to define a standard, consistent way of providing models and information, along with a taxonomy so everyone agrees on the meaning of key terms.

One place to start is with a standard package model format. There is no consistent way to provide electrical modeling and characterization data that could predict signal-integrity problems due to packaging. There are various kinds of 2-D and 3-D models, but the bulk of device vendors provide them very selectively, if at all. It's up to the board designer to interpret what the models mean.

A standardized set of recommended deliverables would also help. That doesn't mean every IC vendor would provide exactly the same set of models and documentation; rather, the vendor would provide a checklist of items that the pc board designer could inquire about. A common taxonomy would ensure that everyone was talking about the same thing.

It would be great if every IC or FPGA came in a nice, clean package with controlled impedance lines for every signal. That's not a cost-effective solution, of course.

But at the very least, designers should know what they're getting and have some chance of determining whether a device will work on their board before they commit to it.

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The Art of Design column offers opinions and perspectives on the technology, techniques and business of electronics design. It covers design automation, test, packaging, boards and silicon. Suggestions or comments may be sent to rgoering@cmp.com.